Study On Dynamic Power Optimization Of Successive Approximation Analog-to-Digital Converter

The majority of the signals in nature are analog signals,thus the use of analog-to-digital converters(ADCs)is indispensable for electronic devices with environmentally interactive ports,and its performance has a vital impactis for the overall performance of the system.ADCs are widely used in the field of wireless sensor networks and medical care electronic devices for long-term monitoring of signals,so it’s necessary to use energy-efficient ADCs to extend battery life in these electronic devices.Successive Approximation(SAR)ADC,as an architecture with medium sampling speed and medium resolution,is mainly composed of digital circuits,which can operate at ultra low power supply voltage to achieve ultra low power consumption.It is widely concerned in the field of low power design.Therefore,the SAR ADC power optimization research has an important significance.In this paper,the overall structure and working principle of SAR ADC are introduced firstly,and the structure of DAC capacitor array is studied emphatically.Based on the analysis of power consumption and linearity of several common switching schemes,a novel SAR ADC capacitor switching scheme is proposed.The scheme uses a partially monotonic three-level structure.During the high-bit comparison process,means of upper plate sampling and capacitive discharge are used,and in the lower comparison process a way similar to a monotonic scheme,which switch only one side of the capacitor in one step,is used to reduce the energy loss of the entire comparison process.The proposed scheme almost work with no energy losing in the comparison process,but most of the energy losing occurs at the reset step.The results show that compared with the energy consumption of the traditional switching scheme,the new scheme can be reduced by 75% and 94.91%,respectively in the use of capacitance area and power consumption.Finally,based on the previous discussion,this paper designs an 8-bit 20KS/s low power SAR ADC under SMIC 0.18μm CMOS process.It uses a double bootstrap sampling switch to cope with situations where the switch can not be fully turned on at ultra low supply voltages to increase the linearity of circuit in this design.By keeping the gate-source voltage constant,the sampling switch on-resistance does not vary with the sample input signal.At the expense of a portion of the input bandwidth,a two-stage pure latch comparator with a pre-amplifier stage is added,eliminating the static operating current of the comparator circuit and achieving lower power consumption.In the logic control module based on the use of dynamic logic control technology to improve the system’s energy efficiency,the use of positive feedback latch as a register circuit to maintain the output of the comparator to reduce the error caused by charge leakage,the use of TSPC trigger as the memory circuit further reduces the static power consumption of the digital circuitry.The simulation results show the performance of SAR ADC designed in this paper at 0.4V supply voltage and 20KS/s sampling rate which achieves SNDR of 44.65 d B,SFDR of 53.76 d B,THD of-48.95 d B and ENOB of 7.12 bit.And the final circuit overall power consumption is 30.27 n W,with the FOM of 10.88 f J/conv-step.