Design Of 10-bit 20MS/s Successive Approximation Analog-to-digital Converter

With the rapid development of wireless communication technology,the application of digital integrated circuits has become more and more extensive,and its role in circuit modules has become more prominent.Digital-analog mixing has become a major trend today.Therefore,as a bridge between the digital circuit and the analog circuit,the analog-to-digital converter(Analog to Digital Converter,ADC)is an indispensable part.At present,the more common ADC types are SAR ADC,Pipeline ADC,Flash ADC,Sigma-Delta ADC and so on.With the use of a large number of mobile terminals,the requirements for the power consumption and area of the ADC are getting higher and higher.Therefore,SAR ADCs with low power consumption,low complexity and a good compromise in terms of accuracy and speed are applied to various mobile terminals,and have become a hot spot in today’s research.Based on a typical application,this article designs a medium-precision,medium-speed SAR ADC,and achieves the requirements of low power consumption.The design adopts a differential structure.The differential structure can suppress common mode interference,effectively increase the dynamic input range,reduce noise,cancel part of the charge injection,and eliminate even harmonics.The DAC capacitor array adopts an energy-efficient switching scheme,which can effectively reduce power consumption and save chip area.The successive approximation logic circuit is composed of a dynamic logic unit array,and the dynamic logic unit is mainly composed of a trigger circuit and a latch circuit.Traditional logic circuits include modules such as shift registers,data registers,and output registers,which require the use of a large number of D flip-flops.The dynamic logic control unit proposed in this paper requires fewer transistors,and the structure of the logic control circuit is simple,which can effectively reduce the power consumption and complexity of the SAR ADC,and at the same time improve the conversion speed of the logic control circuit.The comparator adopts a two-stage structure with pre-preamplification,which is beneficial to reduce the offset voltage,improve the speed and accuracy of the comparator,and isolate kickback noise.The gate voltage bootstrap sampling circuit adopts a capacitor pre-charging method to provide a high voltage for the gate of the sampling switch.The digital code parallel output circuit converts the SAR logic serial output digital code into parallel output,which is mainly composed of an AND gate array.The dynamic logic circuit latches each converted digital code.When a conversion period ends,the EOC end signal changes to a high level,triggers the parallel output array,and outputs the parallel digital code.The asynchronous clock generation circuit is composed of a gate circuit and a delay circuit.The pulse width of the clock must meet the requirements of the DAC setup time.The pulse width of the clock can be controlled by adjusting the delay unit.Based on the 55 nm CMOS process,this paper implements a 10-bit,20MS/s SAR ADC with an effective number of 9.56 bits,a signal-to-noise distortion ratio of61.37 d B,a spurious-free dynamic range of 71.16 d B,and a total harmonic distortion of-75.04 d B;In terms of static parameters,differential nonlinearity DNL=-0.41/0.67 LSB,integral nonlinearity INL=-0.72/0.84 LSB,total power consumption is 0.68 mW,quality factor FOM is 55 fJ/Conv.