Design Of A Low Power SAR ADC And Research Of Switch Switching Scheme

The shrinking of CMOS process size has promoted the rapid development of the integrated circuit industry.At present,integrated circuit products have been widely used in various fields of life as the most important component in integrated circuit systems:analog to digital converters(Analog to Digital Converter,ADC),which realizes the conversion of the original analog signal to the digital signal in nature,and has an irreplaceable role.Among various types of ADCs,successive approximation analog-to-digital converters(SAR ADCs)have been widely applied to medium-high accuracy and medium-speed applications due to their unique advantages of simple structure,low power consumption,small area,and compatibility with advanced CMOS processes.The preferred structure is widely used in many fields such as industrial control,data acquisition,medical equipment,and portable electronic devices.In this thesis,based on 130nm CMOS technology,a low-power SAR ADC with 12-bit precision and 2MS/s conversion rate is designed.Its sub-circuit module is made up of sample and hold circuit,comparator,capacitor DAC array and logic control circuit.Among them,the sampling switch with bootstrap structure is adopted to improve the linearity and reduce the harmonic distortion;combined with a high-efficiency switch-switching DAC array,which reduces the area of the capacitor and effectively reduces the The dynamic power consumption of the switching process;the comparator which is operated under the control of the clock is composed of two-stage dynamic comparator;and the static current of the comparator is is zero.Besides,a dual-supply technology has been used in the ADC,the application of 3.3 V analog supply voltage increases the processing range of the signal with a higher signal-to-noise ratio;and the dynamic power consumption of the digital circuit has been reduced with the supply voltage of 1.2 V.On the Cadence software platform,the design of the overall circuit was performed,and simulation verification with Spectre has been completed for the circuit.Finally,the layout and post-simulation were completed.At a sampling frequency of 2MHz,with the input signal frequency of 901.4kHz,an effective accuracy of 11.58 bits is achieved,the spurious-free dynamic range is up to 78dB,the power consumption is less than 350uW,and the figure-of-merit(FOM)of the ADC is 55fJ/conversion-step.In addition,the capacitive switching procedure was studied and an improved energy-efficient switching procedure has been proposed in this dissertation,the capacitance area is reduced by 75%and the switching power is reduced by 99.23%when compared with the traditional structure,it is of great significance to the research of low-power SAR ADC.