A 10-bit Low-power SRA ADC In 65nm CMOS

With the development of modern science and technology, the implantable biomedical equipments have become one of the hottest research directions. Compared with the traditional portable medical equipments, these devices are more flexible and very important for the diagnosis and treatment of some diseases. However, it is too challenging to make implantable medical devices more secure and stable. For bio-medical applications, the shapes and sizes of these implanted chips are limited by the surgical operation and the heat generated from power consuming can damage the biological issues. Due to the simple structure, small area and low power consumption, successive approximation register (SAR) analog-to-digital converter (ADC) has been widely used in bio-medical electronics. In this thesis, design techniques are proposed to optimize the power and area of SAR ADC for implantable biomedical chips.A 10-bit low power SAR ADC is realized in this thesis. It is mainly composed of Sample/Hold circuit, digital-to-analog conversion network, comparator and SAR logic control circuit. Different structures and the non-idealities of the sub-blocks in SAR ADC are discussed. To satisfy the low-power requirement of the implantable bio-medical chip, novel circuit structures and optimization techniques are used during the SAR ADC design.1. Considering the capacitor array can work without any static power, charge redistribution structure is the most popular structure of low-power SAR ADC. In this thesis, capacitor array structures and switching schemes are discussed at first, then a novel D/A conversion network and switching scheme based on the segmented capacitor array is proposed to reduce the power consumption and area of SAR ADC.2. Fully-differential structure with top-plate sampling is utilized to design the 10-bit SAR ADC. The fully-differential structure is insensitive to the common-mode interference. In addition, the top-plate sampling technique can reduce the size of the input capacitor array, making the power and area of SAR ADC reduced obviously.3. For the other sub-circuits, bootstrapped switches are used for sampling the input analog signal. With constant on-resistance, high linearity of the sample circuit is achieved. The comparator of SAR ADC is designed with two cascaded dynamic structures, which can effectively reduce the static power consumption. The SAR logic control circuit is realized by using dynamic logic circuits. This makes the complexity of the logic circuit in SAR ADC dramatically reduced.With these above techniques, a 10-bit SAR ADC is implemented in 65nm CMOS technology. The ADC is designed with Cadence and simulated with Matlab. With 0.8V power supply and reference voltage, the SAR ADC achieves SNDR (Signal-to-Noise-and-Distortion Ratio) of 61.42dB, when the sampling rate is 50KS/s and the input frequency is 1.5KHz. The ENOB (Effective Number of Bits) of the designed SAR ADC is 9.91 and the power consumption is only 423nW. The FoM (Figure of Merit) is calculated to be 8.7fJ/Conv. step. The layout area of this SAR ADC is 136 μm × 176 μm, making it very suitable for bio-electronics application.