Design Of 10bit 500KS/s Low Power SAR ADC

Benefiting from the rapid development of CMOS technology,wearable biomedical devices and wireless sensor networks have developed rapidly and have improved people's daily lives.These equipments are widely used and require long-term work and try to avoid frequent battery replacement.Therefore,low cost and low-power analog-to-digital converter(ADC)is essential.To meet the above requirements,a 10 bit 500KS/s low-power successive approximation register analog-to-digital converter(SAR ADC)has been designed.Recent research in the field of low-power SAR ADC at home and abroad has been introduced from aspects of switching scheme,capacitor digital-to-analog converter(CDAC)structure and comparator.Then from the system level,a new switch scheme based on improved segment structure,three-level switching,and redundant bit switching is proposed which can significantly reduce power consumption.By using MATLAB to model and simulate the proposed switch scheme and ADC,the feasibility of the method is verified.Compared with the traditional switching scheme,the proposed switching scheme reduces the energy consumption by 98.98% and the number of unit capacitors by 93.75%.To solve the reset problem of the capacitor array during corner and temperature simulation,a charge pump reset circuit is designed.Considering the impact of charge injection,a bottom plate sampling method is applied with the sampling switch.A dynamic comparator based on cascode and tail capacitor is proposed to improve power consumption and noise performance.In the digital circuit part,synchronous timing is used.The SAR ADC's schematic and layout are designed with TSMC 40 nm CMOS process with the die area of 180?m×120?m.At power supply of 0.6V,the post-simulation has been carried out when sampling rate is 500KS/s and input sinusoidal signal frequency is248.5352 kHz.Results show that effective number of bits(ENOB)is 9.93 bit while signal-tonoise plus distortion ratio(SNDR)and spurious-free dynamic range(SFDR)reach 61.55 dB and74.59 dBc,respectively.The total power consumption is 0.825?W,and the figure-of-merit(FoM)is 1.69 fJ/conversion-step.The proposed SAR ADC meets the design specifications.