Design Of High Speed Pipelined ADC Using Open-loop Redundant Structure

With the advancement of wireless communication technology,as the part of communication system,ADC is becoming more and more important.Compared with other architectures of ADC,Pipelined ADC can achieve high speed,high accuracy and low power consumption.This is in line with the development requirements of wireless communication.So,it has great research values.Pipelined ADC designed in this paper is used in the field of wireless communication.According to study the research status of pipelined ADC,and analyze the advantages and disadvantages of open-loop MDAC and closed-loop MDAC,this paper proposes open-loop MDAC based on the redundancy to design pipelined ADC.In order to solve the poor linearity and low accuracy of open-loop amplifier,a look-up digital back-end calibration technique is used to process the comparator offset and inter-stage gain error.This improves the accuracy of ADC obviously.In addition,Pipelined ADC designed is consist of 14-stage circuits(Each circuit is called 1-bit/stage circuit),layout design can be simplified by copying the layout of first stage circuit.On the basis of determining the circuit structure,Simulink modeling is used in this paper to verify the feasibility of redundant open-loop structure in circuit implementation.Modeling simulation shows that SNDR is 27.05dB,SFDR is 29.72dB,and ENOB is 4.2 bit when the frequency is 47.65625MHz,and the sampling rate is 100MHz.After calibration,SNDR is 74.51dB,SFDR is 82.05dB,and ENOB is 12.09 bit.Pipelined ADC implemented in TSMC 0.18?m 1P6M CMOS technology.The power voltage is 1.8V.The entire circuit mainly includes 14-stage circuits and delay alignment register arrays.Each stage circuit is made up of S/H circuit,sub-ADC,MDAC and clock circuit,layout area is about 1.2mm× 1.4mm.The maximum input signal swing is 600mV,the sampling rate is up to 100MHz,and the accuracy is 12 bit.The post-simulation shows that SNDR is 26.66dB,SFDR is 29.65dB,and ENOB is 4.136 bit when the amplitude of input signal is 600mV,the frequency is 47.65625MHz,and the sampling rate is 100MHz.After calibration,SNDR is 68.98dB,SFDR is 78.98dB,ENOB is 11.17 bit and power is 155mW.