| Pipelined ADCs are widely used in communication and image processing systems, as they can achieve high speed data conversion and high resolution. But in recent years, with the decreasing supply voltage and the constraint in deep submicron technology, power consumption is becoming the biggest obstacle of pipeline ADCs. This paper is concerned with the key building block MDAC and its OTA cell in a 12bit 100MSPS pipelined ADC and with the purpose of decreasing power consumption with an open-loop structure.Compare the open-loop MDAC with the traditional close-loop MDAC from the working principle and circuit structure. Analyze the close-loop structure's advantage and disadvantage from the relationship between speed, resolution and power consumption under lower supply voltage and deep sub-micron technology constraints. Study the power consumption advantage of open-loop structure with digital correction under the condition of decreasing supply voltage and reducing intrinsic transistor gain.In the circuit realization of open-loop MDAC, the OTA cell with source degeneration and a further tail current fitting by cross-coupled pairs can meet the requirement of linearity. Besides, a gain control circuit will be added to prevent the gain variance from the variance in temperature, technology and environment, also to compensate the gain reduction causing by parasitic capacitance.Based on the 0.18μm/3.3V silicon CMOS process model, the MDAC and OTA cell have been simulated in Cadence simulation environment. The results show that, the first-stage 3.5 bit open-loop MDAC reaches settling final value of 499.82mV at the settling time of 4.06ns; The OTA cell HD3 is -67.65dB; The total static power dissipation is 8.71mW, usually with the traditional structure is 40mW.Lastly, accomplish the layout of open-loop MDAC with 0.18μm 2P4M CMOS process.Therefore, the open-loop MDAC can save power consumption efficiently and fulfill the system requirements of 12-bit 100MSPS pipeline ADC. |
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