GS/s Pipelined A/D Converter Based On Open Loop Redundancy Structure

With the rapid development of modern communication technology,the requirements of communication system for data transmission rate are more and more high.As the core module of data conversion,the performance of ADC will directly limit the data transmission rate.Pipeline ADC can achieve high-speed,middle and high precision performance,meet the needs of the development of communication technology,has a certain research value.The research status of high-speed ADC at home and abroad is investigated,the implementation scheme of high-speed pipeline ADC is understood,the inherent defects of traditional closed-loop structure and its improvement scheme are analyzed in detail,and the overall ADC implementation scheme is determined.The open-loop structure is adopted to achieve high sampling rate while reducing the power consumption.Single stage gain attenuation is set to improve the tolerance of comparator offset,amplifier offset and inter stage gain deviation.Adding two redundant stages to ensure a certain accuracy,using digital background calibration to improve accuracy and reduce power consumption.The feasibility of this scheme is verified by MATLAB behavior level simulation,and the accuracy can reach 8bits at 1GS/s sampling rate.Next,the sub module circuit is selected,the first stage ADC uses high-speed gate voltage bootstrap switch to improve the accuracy,and the sample and hold circuit adopts fully differential structure with bottom plate sampling technology to reduce the influence of nonideal factors such as charge injection and clock feedthrough.The residual amplifier adopts total transconductance migration technology to enhance the swing of the ADC signal;The discrete common mode feedback circuit is adopted,which does not limit the swing of the input signal,does not introduce extra zeros and poles,and reduces the complexity of the circuit;A two-stage dynamic comparator with only three stacked transistors is used to realize high-speed comparison and low-voltage operation;The ADC modules at all levels are highly repetitive,and can be copied and used with a little modification after the first level design,which greatly reduces the workload.The design is based on TSMC 45nm 1P10M CMOS process,and the power supply voltage is 0.9V.The whole circuit has 10 stages,using single bit per stage structure,completed the circuit schematic design and pre simulation,layout design and post simulation.Symmetry,reliability and anti-interference are considered in layout design.The overall layout area is660×8508)~2.When the sampling rate is 1GS/s and the peak to peak value of the input signal is 600m V,the post simulation results show that when the input is 496.09375MHz,the dynamic parameters SNDR is 25.66d B,SFDR is 30.72d B and ENOB is 3.97bits before calibration,after calibration,the dynamic parameters SNDR is 43.44d B,SFDR is 54.28d B and ENOB is6.92bits and the overall power consumption is 44m W at 27? in the tt corner.