Research And Design Of A 10bits 60MSPS Pipelined ADC

With the rapid growth of wireless communication systems and portable video device, the demand for low-power and high-speed integrated circuits is indispensable. The analog-to-digital converter is a performance critical component in these applications. In order to meet demand, the analog-to-digital converters (ADC) are increasing their sampling rate and reduce power dissipation. Among many types of CMOS ADC architectures, the pipelined architectures can achieve good high input frequency dynamic performance and as a high throughput. The aim of this thesis is to investigate the design techniques of pipelined ADC for high sampling rate applications. The targeted architecture is a 10-bit, 60Msampling/s pipelined analog-to-digital converter.The pipelined ADC consists of the building blocks like sampling-and-hold circuits, 1.5bit/stage sub-ADC, sub-DAC, gain stage, digital error correction logic circuits and clock generator. Considering the speed, power dissipation and specifications, a flip-around sample and hold circuit was designed to reduce the power consumption; The pipelined ADC is followed by eight 1.5-bit stages and a final 2-bit flash sub-ADC. A digital correction circuit is used to eliminate errors between every stage; in sample and hold circuit and Multiplying DAC, a gain-boosting cascade op amp was used to insure the speed and precision of the Switch-capacitor circuit. A latch comparator with pre-amp has been used to reduce the kick-back effect. The design is based on Chartered 0.35um CMOS mixed-signal library, and the power supply is 3.3V. The results indicate that the analog input of ADC range from 1.15V to 2.15V, its sample rate is 60MHz, power consumption is about 130mw and the parameters of the whole sub circuits meet the design requirements.