High Precision In Pipeline Adc Sampling Keeping Circuit And The Design Of The Mdac

Although more and more signal-processing functions are implemented in digital domain, ADC as the link between analog world and powerful digital systems is an indispensable module in mixed-signal processing systems. For higher integration, there is great demand for ADC that can be implemented in the same main-stream CMOS process with digital processing circuit.With the advancement of deep-submicron process, digital circuit can be realized with smaller area, lower power and higher frequency. But it’s different for analog circuit design, the lower intrinsic gain and power supply voltage accompany with short channel device propose more and more challenges. In order to satisfy the precision and speed specifications of the system, the analog designers have to explore new system and circuit architectures.Pipelined ADC composed of some cascade low resolution sub-ADCs and taking OPAMP-based switch capacitor (SC) circuit as core module is the predominant architecture to realize high-speed high-resolution ADC, and is also the hot spot in industry and college research.This thesis addresses the non-idealities and difficulties in the design of pipelined ADC with short channel and low power supply. The research achievements include (1) a multi-bit per stage ADC architecture. With the4+4+4+3-bit architecture, the latency is reduced,(2) a nested gain-boosted folded-cascode amplifier. With carefully design of the bandwidth relationship between the main amplifier and the auxiliary amplifier, the nested gain-boosted amplifier obtains a high gain with large unity gain bandwidth (UGB). Pre-simulation shows that, the DC gain is over90dB, the UGB is4.75GHz and the phase margin (PM) is55°under typical CMOS process corner,(3) the merged S/H and first MDAC (SMDAC) technique eliminates the dedicated S/H amplifier, successfully avoids the power dissipation and extra noise,(4) to further reduce power and area, OPAMP-sharing between successive stages is employed.Under Cadence IC61design environment, key modules of the prototype ADC such as the nested gain-boosted amplifier and the SMDAC were implemented with IBM 0.13μm CMOS process. Post-simulation results show that the SMDAC based on the nested gain-boosted amplifier statisfies the accuracy-and speed-requirement of12-bit100-MS/s ADC.