A First-stage MDAC For16-bit Pipelined ADC Without S/H Circuit

With the increasing of the demand of mixed-signal system performance, as a keypart in the mixed-signal system, high-precision, high-speed, digital-to-analog converters(ADC) based on standard CMOS technology are also under rapid development. Inaddition, lower power consumption, lower supply voltage, and the smaller the area hasalso become the core area of the ADC design. Pipelined ADC is suitable for high-speed,high-precision applications. However, the sample and hold (S/H) circuit in pipelinedADC system takes up too much power consumption.In response to these problems, this paper proposed a pipeline ADC structurewithout S/H circuit. The main contents are as follows:1. Studied the Pipelined ADC architecture and performance parameters, and thefactors affecting the performance of pipelined ADC and its solution.2. By analyzing of the structural characteristics as well as the working principle ofthe MDAC, and the corresponding mathematical model, a MDAC structure without S/Hcircuit is proposed. For this feature, this paper proposed a new structure to solve thisquestion, by decreasing the gain of the first stage MDAC and increasing the gain of thesecond stage MDAC, and improved the ADC’s correction range.3. Based on the ADC architecture without S/H circuit, this paper finished thedesign work of the first stage MDAC. For the residual amplifier with wide bandwidthusing gain-boost structure, the unity gain bandwidth was up to2.45GHz; For thecomparator, this article uses a structure that can be quickly reset, increasing the residualamplifier settling time margin; Further, in order to solve the nonlinear problems of theCMOS sampling switches, the gate voltage bootstrap switch structure is used.