A Study Of 10 Bit 250MS/s Asynchronous SAR A/D Converter

With the development of microelectronics technology,more and more traditional circuits are integrated into the chip,and medical devices and a variety of consumer electronics products continue to shrink the size.With the development of digital signal processing system,the requirement of high performance data converter is increasing.SAR ADC completing the data conversion based on binary searching algorithm,compared with other structures of the ADC,has a very big advantage in the area and power consumption.SAR ADCs have been widely used in sensor networks,biomedical,video,wireless communication and many general purpose applications.The working principle of various structure ADCs have been analyzed and compared in this thesis.We first present an extensive study on the key functional block in the SAR ADC.The working principle and the non-ideal effects of the high linearity sampling circuit have been analyzed.The implementation of DAC network has been described.This thesis has also analyzed the operation of the high-speed dynamic latch comparator,and the variation of digital logic.Finally,this thesis has optimized the three decisive components of one comparison cycle delay: DAC settling time,the delay of the comparator and digital logic.To guarantee the stability of the voltage between the gate and the substrate during the sampling,the traditional high speed and high linearity bootstrapped switch is improved,thus eliminating the potential breakdown of the circuit.The application of the split capacitor array makes the settling time and area significantly decreased,compared with the traditional capacitor array.The switching sequence adopted in this work can achieve a constant common mode voltage,and simplify the design process of subsequent logic circuit.A behavioral model simulation in Matlab is proposed to verify the linearity of the proposed switching sequence.The comparator asynchronous clock circuit is presented,and a dynamic comparator reset time technique is employed.A different time of the comparator reset phase is distributed based on the different DAC settling time,thus avoiding a waste of time caused by the small capacitance,and further shorten the comparison cycle.A dynamic latch comparator is introduced,and the delay,offset and noise of the comparator are analyzed.The dynamic SAR logic control circuit is adopted to reduce the power consumption of the digital circuit and shorten the delay of the digital logic.Finally,the analysis and optimization of the layout are presented.A 10-bit 250MS/s SAR ADC is designed and taped out in SMIC 55 nm 1P6M digital CMOS technology.The core area of the ADC is 280?m×380?m.The measurement results show that the DNL and INL of the proposed SAR ADC are +0.6/-0.38 LSB and +0.46/-0.82 LSB at 1.2V supply voltage and 250MS/s,respectively.Dissipating 3.43 m W at 1.2V supply voltage,this design achieves an SNDR of 56.5d B,an SFDR of 63 d B,and an ENOB of 9.09 bits on condition that the input signal is Nyquist frequency,and the amplitude is-1.5d BFS.This corresponds to a figure-of-merit(Fo M)of 25 f J/ conversion-step.The SNDR is always more than 56 d B in the entire Nyquist interval,which means the ENOB is greater than 9 bits.