| With the development of digital signal processing technology in today’s society, the digital circuit with its absolute advantages such as flexible design, low cost, and strong anti interference ability, easy to integrate, easy to handle gradually replacing analog circuits become the mainstream of IC design, is used on medical equipment,communication, image and other fields. Therefore, the ADC as the conversion circuit from analog signal to digital signal has become a top priority, in all types of ADC, the successive approximation ADC(SAR ADC) has favored by people with its simple structure, small area, low power consumption, easy integration and other advantages.However, although the successive approximation ADC can achieve ultra-low power consumption, the speed is lower than other types of converters, and therefore enhance the speed of SAR ADC conversion has become an urgent matter, through asynchronous timing control analog to digital conversion is a good way to enhance a converter’s speed.This thesis designed a successive approximation ADC, and the use of asynchronous control technology has greatly enhanced the speed of the converter. Successive approximation ADC designed in this thesis include sample / hold module, a comparator module, DAC module, SAR logic control module and an asynchronous clock generation module, and each module is designed and analysis specifically, three kinds of switch timing analysis at the same time, and gives the advantages and disadvantages of each switch timing. Among them, the sample / hold circuit determines the accuracy of the entire SAR ADC system as the starting ADC, we used a bootstrap circuit in this study to make the gate-source voltage of sampling switch fixed, reduced nonlinear error caused by the on-resistance and the differential structure enhance the accuracy more. The accuracy of the differential type bootstrapped switch in this study reached 10.63 bit through the simulation, fully meet the 8 bit digital converter in this subject; The speed of comparator is extremely important for the whole system, because of the greater the latch input signal voltage, the higher the speed, so we first amplified the input signal by a preamplifier and then enter the both ends of the latch latches, it will shorten the response time of the latch and enhance the conversion speed by this way. The comparator of this subject can identify 2mv difference voltage by the simulationanalysis and can meet the overall system requirements; DAC module using charge redistribution technology, sampling by the up plate of the capacitor array, re-distribution the charge according to the principle of charge conservation, and control the capacitive switches by SAR logic control module, maintain a differential comparator input by using a symmetric switch timing; A feedback formed between the asynchronous clock generation module and the comparator module, control the comparator module and the SAR logic control module according to the output of the comparator, to make the comparator and DAC module enters the following cycle comparison process immediately while the cycle of the comparison completes, saving the time of the comparator waiting for a fixed clock cycles, improve the conversion rate, and reduces the power consumption because the avoid use of an external high-frequency clock.This thesis designed an 8 bit single-channel high-speed asynchronous SAR ADC based on SMIC 65 nm technology, and at 1.2V supply voltage, the sampling rate of 303 MHz,the sampling points to 1024 points, SAR ADC’s SNDR is 49.65 d B, SFDR is 67.44 d B,and ultimately achieve effective number of bits is 7.95 bit by spectral analysis. The SAR ADC designed in this thesis has excellent performance and can meet the demand by the simulation. |
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