High-speed clock and data recovery circuits in CMOS technology

The evolution of the optical fiber to high speed, low cost data transmission media led to the Synchronous Optical Network (SONET) standard in North America and to the Synchronous Digital Hierarchy (SDH) in Europe. With the exponential growth of the Internet nodes and, hence, the need for a media with low cost and high band-width, the use of optical fibers is increasing rapidly.; The optical transmitter converts electrical pulses to optical pulses. Ultra-pure glass fiber is the medium used to guide light pulses. The optical receiver converts optical pulses to electrical ones. In order to sample the continuous time received signal and convert it to a discrete time sequence, the receiver needs an in-phase clock at the symbol rate. A clock and data recovery (CDR) circuit extracts the necessary phase information from the data. The CDR circuit is complex, and the design of such systems for high data rates is challenging.; In this dissertation, a CDR circuit for multi-giga-bits serial data communication was designed and fabricated in a 0.18mum CMOS technology. Jitter peaking phenomena of the existing CDR systems have a destructive effect on digital repeater chains. Design and implementation of a CDR architecture that theoretically produces no jitter peaking were the ultimate goals of the research. Such a CDR system was designed and fabricated. The proposed CDR system was proven analytically and by measurement to produce no jitter peaking.; Among the test circuits implemented was a 3--11GHz voltage controlled oscillator (VCO). The proposed VCO consists of two two-stage ring oscillators that are coupled to each other. It has been proven analytically that the coupled two-stage ring oscillator is faster than other types of ring oscillators. A linear and a three-state digital phase detector as well as a frequency detector, suitable for high speed CDRs, have been proposed and implemented. Simulations and measurements show that the three-state phase detector has improved performance for high speed applications.