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8-bit High Speed SAR ADC Design

Posted on:2015-02-22Degree:MasterType:Thesis
Country:ChinaCandidate:Q Y WangFull Text:PDF
GTID:2298330431464241Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With high-speed development of digital technology, especially development ofcommunication technology, digital circuits are widely applied to communication,detection and control. There are more and more requirements of transformation fromsignal to digital, while the analog digital converter is the key of transforming fromanalog signal to digital signal. There is a higher request for the speed, resolution,consumption and SNR of ADC. With low power consumption, small size and highenergy efficiency features, the SAR ADC is widely used in high speed transformation,portable medical equipment and batteries, etc.On the basis of comparing and analyzing the characteristics of the different ADCs,SAR ADC has been chosen as the emphasis of the thesis. An8-b208MSPSsynchronous SAR ADC and an8-b660MSPS asynchronous SAR ADC are presented inSMIC65m CMOS technology. A reused terminating capacitor switching procedure isproposed in both SAR ADCs to achieve a high-speed and low-power operation, and apre-settlling procedure is proposed in the asynchronous SAR ADC to relax the settlingtime. Besides that, in order to improve the speed and accuracy, a high speed comparatorwith offset calibration is also proposed in this thesis.At a1.2-V supply and208MS/s, the synchronous SAR ADC consumes2.7mW andachieves an ENOB of7.95dB. The FOM of the synchronous SAR ADC is52.4fJ/conv.What’s more at a1.2-V supply and660MS/s, the asynchronous SAR ADC consumes7.6mW and achieves an ENOB of7.94dB. The FOM of the asynchronous SAR ADC is46fJ/conv.
Keywords/Search Tags:SAR ADC, high speed ADC, reused capacitor, asynchronous clock, pre-settling procedure
PDF Full Text Request
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