Design Of 14-bit Successive Approximation Analog To Digital Converter

Nowadays,digital signal processing technology is in a stage of rapid development,ADCs(Analog to Digital Converters)have also received more attention and application as the "bridge" of analog and digital signal.Among them,SAR(Successive Approximation Register)ADCs are renowned for their prominent energy efficiency,as the CMOS technology continues to evolve and the size of the process shrinks,the advantages of SAR ADC in speed and power consumption are even more significant.SAR ADCs have been widely used in sensor networks,biomedical custom integrated circuits,video,and many common areas of life.In this paper,the overall architecture of SAR ADC is introduced and the design method of each circuit module is discussed.A 14-bit 5 MS/s split SAR ADC based on the principle of charge redistribution is designed in this thesis?Since the total capacitance of the successive approximation analog-to-digital converter is exponentially related to the ADC resolution,the total capacitance and chip area will increase dramatically for the higher precision SAR ADC,and the dynamic power dissipated when the switching capacitor is switched consumption also increases.Therefore for high-precision capacitive ADCs,it is usually necessary to use large capacitors,which results in a large charge and discharge power,a large area required for the production of the chip,and an increase in economic costs.At the same time due to the increase in the accuracy of ADCs,capacitor mismatch,comparator error and so on for the analog-todigital converter greater impact,which are limited to SAR ADC design.The split capacitor array is used in this design,compared with the conventional SAR ADC with the traditional capacitor array,the split capacitor array uses less capacitance,correspondingly saving the area and the cost of the chip.At the same time,in order to reduce the influence of capacitance mismatch,comparator's error comparison and other factors to the whole SAR ADC,based on the split capacitor array,the SAR ADC described in this paper uses redundant capacitor array design.This design uses 0.18?m 1P4 M CMOS technology,the overall chip area is 500?m ×500?m?The total power consumption of the ADC is 1.19 mW at a 1.8V supply voltage.When the sampling clock signal frequency is 5 MSPS and the input signal frequency is 2.43652 MHz,the circuit simulation results are as follows: the effective number of bits(ENOB)is 13.65 bit,the signal-to-noise distortion ratio Signal-to-Noise and Distortion Ratio(SNDR)is 84.0 dB,and the Spurious Free Dynamic Range(SFDR)is 88.2 dB.