Research And Design Of 12-bit High Speed And Low Power SAR ADC Based On CMOS Process

Today's society has entered the "artificial intelligence" era.Digitization degree is higher and higher with the progress of technology,ADC is the connecting link of analog signal and digital signal,are indispensable in the electronic system.In recent years,the consumer market huge demand for portable electronic products,intelligent wearable devices with low power consumption and high integration of electronic systems,which has low power consumption,high speed,high precision ADC technology has become a hot spot of research and development.At present,the mainstream manufacturing process of IC is 90 nm to 65 nm,the most advanced achieved the process of 28~14nm.Successive approximation Register analog-to-digital converter(SAR ADC)has the advantages of low power consumption,low cost,simple structure,small chip area,high degree of digitization,making it more adapt to the development of the process requirements.In this paper,the contents and objectives of research are clarified,and describes the development status of successive approximation analog-to-digital converter(SAR ADC)under nanometer process;introduced the working principle and typical structure of SAR ADC,ultimately determine the use of sub-capacitor array structure design;furthermore,study on energy consumption analysis and matching of capacitor array,calculate the specific parameter.Designed and completed a 12-bit,sampling rate of 80 MSPS asynchronous SAR ADC circuit,in the standard of 65 nm CMOS process,which including sample and hold circuit,capacitor array DAC,comparator,digital logic control module,after the completion of theoretical research.According to the design indexes of the 12 bit,the two weights capacitor array structure is determined,and the capacitance array is divided into a high order 7 bits and a low order of 4 bits,which reduces the total area of the capacitor and reduces the power consumption of the DAC.The split monotonic scheme is used to reduce the number of the capacitor state changes and reduce the total power consumption.Bootstrap technology is used to design highly linear sampling switch.The dynamic comparator with pre amplifier and Latch comparator is used to improve the conversion speed and reduce the power consumption.Optimizing D trigger to improve asynchronous logic structure.the delay time of shift and latch is reduced,the speed of the whole circuit is improved,and the power consumption is reduced.In the conditions of working voltage of 1.2 V and sampling rate of 80 MSPS to simulate the whole circuit.the spurious free dynamic range(SFDR)is 86.54 dB,the distortion of signal-to-noise ratio(SNDR)of 68.46 dB,the effective number of bits(ENOB)reached 11.08 bit,the total power consumption for 2.352 mW.The results show that this design of SAR ADC can reach the indexes of the paper design requirements.Finally using Cadence Virtuoso complete the ADC circuit layout design,drawing and parameter extraction.