High speed submicron CMOS oscillators and PLL clock generators

This thesis presents the design, analysis and implementation of monolithic GHz range voltage/current controlled ring oscillators and a monolithic phase-locked loop (PLL) clock generator in submicron CMOS technology. A general ring oscillator topology capable of achieving high speed operation, multiphase output and wide tuning range is proposed. The topology uses sub-feedback inverters to construct fast loops enabling a long chain ring oscillator to achieve increased operating frequency and higher equivalent quality factor. The operating frequency of the ring oscillator is directly proportional to the transconductance (Gm) of sub-feedback inverters which can be controlled with an external voltage to achieve linear tuning. Detailed implementation of the topology for both single-ended and differential circuits is also proposed. Extensive theoretical analysis yielded insight into the sub-feedback loop ring oscillators and allowed formulation of design guidelines. Simulations and measurement results (0.5 mum CMOS process) support the analytical findings. A fully integrated 1.25 GHz 0.35 mum CMOS PLL clock generator that included the proposed VCO topology and a frequency control and stabilizing bias circuit was designed, implemented and tested. Measurement results confirm the suitability of the VCO and the PLL for applications such as clock generation/recovery systems, high speed multiphase data sampling and microprocessor clock synchronization.