Research On 16-bit 1MSPS SAR A/D Converter

Compared with pipeline analog-to-digital converters and Sigma-Delta analog-to-digital converters,Successive approximation register analog-to-digital converters(SAR ADCs) are widely popular in medium-speed medium-high-resolution applications due to its simple structure,low power,small size,easy integration,etc. High resolution SAR ADC is widely used in biomedical devices such as CAT scanners, portable blood analyzers, nerve sensing and in industrial imaging and wireless communications.Nonlinear error caused by capacitor mismatch is a main factor affecting the accuracy of the SAR ADC. In standard process, the effective number of bit(ENOB) is below 12 bit in SAR ADC without calibration or trimming. However, the emergency of calibration improves ENOB of SAR ADC. In industrial, laster trimming and special process are used to improve the accuracy of capacitor matching and then calibration techology is applied to calibrate the error by capacitor mismatch. Compared with tranditional analog calibration methods, digital calibration methods have an advantage of high integration, small size, and quicker convergence. Therefor the digital calibration technology becomes the mainstream among various calibration technologies.The principle of SAR ADC is introduced in this thesis. The performace parameters are analysed and the basic thougth and operational principle of split ADC are detailedly discussed. A brief introduction of various redundancy calibration algorithms is presented and then the calibration condition of ADC weight is derived. In order to reduce effect of harmonics by capacitor mismatch, a novel ideal that DWA algorithm is used in DAC network is proposed to achieve the ADC output first order shaping. Through the analysis of tranditonal split ADC calibration techology, a improved Jacobi iteration method is put forward, which is brief structure, less hardware and easy to implement. Because of DWA algorithm, the split ADC calibration algorithm extractes information for various signals, such as a DC signal, random signal, a continuous signal and a non-continuous signal. On the basis of behavioral model of ADC structure, split ADC calibration algorithm and verification, calibration algorithm begins to converge, and the weighte error is in the 0.5LSB range, after 600,000 times conversions. Before callibration the DNL and INL were 1.5LSB, 20 LSB, and after calibration ADC's DNL and INL are within 0.5LSB range, which means the static characteristics are improved. In addition, the paper analyzes the principle of boostrap circuit and then puts forward a new bootstrapped switch for bottom plate sample. Subsequently, a novel DAC network with four redundant bits is designed. Finally, the offset calibrations of comparator are shown and a high resolution, low noise comparator with two paths is come up with. Its specifications and simulation results are presented with detailed analysis.This thesis designed a 16-bit 1MS/s SAR ADC circuit based on SIMC 0.18 um 1P6M CMOS process and the power supply voltage is 3.3V. The simulation results show that ADC achieves an SFDR of 102.8d B, an ENOB of 15.53 bit with 0.46582 MHz input signal under a sampling frequency 1MS/s.