The Study Of SAR ADCs And Their Silicon Implementations

With the increasing high integration of chip design,SoC(System on Chip)is widely used in many fields.In some SoCs that interface with the physical world,analog to digital converters(ADCs)are needed in order to utilize the digital signal processing circuits.Two successive approximation register(SAR)ADCs with different performances are designed in this thesis.One is a 1-2-V 10-bit 10-MS/s ADC that can be used in RF receiver baseband signal process;the other is a 3.3-V 12-bit 2-MS/s ADC that can be used in the accelerometer of the closed-loop system,as a part of a gyroscope.The traditional logic algorithm needs to preset the capacitor array to decide which reference voltages to be connected according to the result of the comparator.Based on bottom-plate sampling,this thesis uses a method of shorting the bottom-plate of capacitors after the sampling is completed.This can directly generate the most significant bit(MSB)in the first comparison cycle without presetting.The logic used in this thesis is different from the traditional algorithm,which enables a 9-bit(11-bit)DAC(Digital to Analog Converter)to meet the accuracy requirement of the 10-bit(12-bit)SAR ADC.The DAC uses a segmented capacitor array that can reduce the die size and power consumption.Fabricated in GSMC 0.13?m 1P7M CMOS technology,the two SAR ADCs occupy die area of 500?mx360?m(10-bit)and 880?mx520?m(12-bit),respectively.Measurements of 10-bit SAR ADC show that with a single 1.2-V supply,it achieves 8.45 effective number of bits(ENOBs)and 0.23mW power dissipation with a 2MHz input signal at 10MS/s,and 8.75 ENOBs and 0.22mW power dissipation with a 1MHz input at 5MS/s,which meets the ADC requirement for the targeted RF receiver application.Post simulation results of the 12-bit SAR ADC show that with a single 3.3-V supply,it achieves 11.7 ENOBs and 1.14mW power dissipation with a 200KHz input at 2MS/s,which meets the ADC requirement of for the targeted accelerometer application.