A Study On Key Techniques Of GS/s Time-Interleaved Pipelined A/D Converter

Having a good compromise in terms of speed and accuracy,pipelined ADC attracts attention to people.However,with the rapid improvement of wireless communication technology in recent decades,the speed of single channel pipelined ADC has unable to meet the high-speed development of the whole system,time-interleaved pipelined ADC?TIADC?begin to become a major research hotspot.Utilizing clock distribution to control many ADCs working in parallel,time-interleaved technique realizes the rate of doubling on the premise of meeting the resolution requirement.To reduce the error caused by sampling time mismatch,TIADC in this work is of SHA architecture.On the basis of introducing the single channel pipelined ADC,the TIADC is deeply analyzed and studied to achieve 6-channel interleaved structure finally.In this paper,the basic working principle of single channel pipelined ADC and the architecture of MDAC are introduced,the transfer function is deduced,and the redundant sign digit correction technique which can reduce the quantization precision of sub-ADC is present,and describes the principle of time-interleaved pipelined ADC.Then,some non-ideal effects in single channel are analyzed,including clock feed-through effect,charge injection effect and clock jitter on the performance of the whole converter.And gives their own solutions,including the bottom plate sampling technique and the gate voltage bootstrap technique.Error will be introduced by the limited gain and bandwidth of the amplifier when ADC is established.In order to achieve the accuracy,gain and bandwidth required to meet certain demand.A new type of complementary operational amplifier is designed in this paper.There are three non-ideal effects existing in TIADC,offset mismatch,gain mismatch and time mismatch,and gives the corresponding elimination method.The circuits are physically implemented.S/H consists of a high gain and high bandwidth operational amplifier and bootstrap switch.MDAC includes amplifier,sampling network and sub-DAC,and the sub-ADC consists of comparator array.The single channel ADC is simulated and 6-channel TIADC is carried out.The various mismatches between the channels are calibrated by the calibration techniques to meet the performance requirements.Finally,the layout is drew and complete the overall design.The innovations of this paper are as follows:a new type of structure is proposed by using the global clock,hoping to solve the mismatch of the sampling time from the circuit itself.A high gain and high bandwidth optional amplifier is designed to meet the establishment of accuracy requirements for residual signal in single channel pipeline.By using class-AB type structure,the load of the optional amplifier also as a signal input,thereby increasing the transconductance,increasing the bandwidth.Using dual power supply,the optional amplifier uses 1.8V high voltage to increase the output swing and reduce the impact of linearity on ADC performance,the remaining circuits with 1.3V low voltage power supply,to meet the performance under the premise of reducing power consumption.The ADC designed in this paper is based on the TSMC 65nm 1P9M CMOS standard process,with a total area of 2.73×1.92mm².The circuits are detailed simulated,bootstrap switch sampling a 22.4609375MHz 1.6V_p-p at 500MSps achieves an SFDR of 107.688dB,and S/H circuit is of 100.088dB.The maximum transmission delay of comparator is100.6ps;the single channel ADC achieves SNR of 68.13dB and SFDR of 75.39dB at the sampling rate of 500MHz.The 6-channel time-interleaved ADC achieves SNR of 53.71dB and SFDR of 69.32d B at the sampling rate of 3GHz.