Research And Implementation Of Digital Background Calibration Of Mismatch Of Time-Interleaved Analog-To-Digital Converter

With the development of science and the arrival of information era, the demands for the application of multimedia technology make modern communication systems moving towards high-speed, low power and high-capacity. Analog to Digital Converter(ADC) in modern communication system is evolving to meet the higher performance requirements: Low-Power, High-Speed and High-Resolution at the same time. As a kind of high-speed and high-precision scheme, TIADC gets more and more attention in recent years.However, some kinds of mismatches due to the instability of anolog circuit limit the resolution and reduce the signal to noise ration(SNR). So, mismatch calibration technique of TIADC has been one of the hotspots in this field.First of all, the principle of TIADC and the mechanism of mismatch is introduced in this thesis, and then the cross-impact of several important mismatch errors, including offset mismatch, gain mismatch, clock mismatch, and bandwidth mismatch, is described in detail as well as.on. Summarize on some prior the various existing mismatch error correction algorithms is given.Secondly, based on the earlier research, digital post-calibration techniques are improved in this thesis by means of a low cost and a high-precision algorithm, to apply to different applications.Simulation results show that the mismatch estimation module in low-cost algorithm can save 93% adder and 90% multiplier comparing to the high-precision one, and the correction module can save 45% adders and 47% multipliers than high-precision arithmetic. Meanwhile, because of the nonlinear of bandwidth mismatch can be corrected by the high-precision algorithm, the system SNR improves 25.1809 d B, and the effective number increases 4.1453 bits.To meeting the demand of a specific project a RTL model of low-cost algorithm is implemented on Xilinx XC6VSX475 T FPGA, using fast convolution algorithm for further hardware optimization. The measuring results show that a single channel calibration circuit can stably work with 300 MHz clock signal, four-channel calibration circuit’s throughput can reach up to 14.4Gbps when single-channel data bits wide is 12 bits, a 4-channel 400 MHz of TIADC sampling system PCB was designed and manufactured to furthur verify the calibration algorithm. The result shows that SNR will be improved 50 d B, effectively improve the effective numbers of bits 5.5bits.