Research And Design Of Key Cells In12Bits Pipelined ADC

With the rapid development of communication system and digital signalprocessing technology, the higher requirements of speed and resolution for analogdigital converter are put forward. As pipelined ADC has an excellent combination ofhigh-speed and high-resolution, it has been widely used in electronic products.This paper based on TSMC0.13μm1P8M standard CMOS process, designing alow-voltage pipelined analog-to-digital converter (Pipelined ADC). The first stageplays an important role in determining the performance of the system. This paper willfocus on the designing and implementation of the first stage. The stage of the pipelinemainly consists of Sub-ADC and MDAC, it mainly completes sampling and holding,digital quantification and the function of generating residual signal.The core circuitsare quantizing comparator and operational amplifier. This paper design a type of switchcapacitor preamplifier-latch comparator and a folded cascode as well as gain-boostedskill operational amplifier. The simulation results show that the setup time ofquantizing comparator is about350ps, the Monte Carlo analysis of the input offsetvoltage means for0.14mV, root mean square is6.45mV.The operational amplifierlow-frequency gain is about96dB, unit gain bandwidth is about580M, the phasemargin is about65degrees. The simulation result of the first stage indicates that, theinput range changes from negative500mV to positive500mV, the design circuit of firststage meet the design requirements, and has good performance. Besides, the test resultsshow that the Pipelined ADC adopting this first stage circuit realizes the basicfunctions, and achieves good characteristics of THD and SFDR.