Research And Design Of CPPLL Based On Fractional-N Divider

Frequency synthesizer based on phase locked loop(PLL)has been widely used in the national life and military fields,such as computer,radar,communication,space exploration,space navigation,etc.In addition,the PLL can also be used to generate local oscillation signals in wireless communications,can also restore the original data from the baseband modulation signal receiver,can be flexible to modulation and demodulation circuit different.The development trend of digital analog hybrid circuit is very fast,so the structure of the Hybrid PLL is becoming more and more diversified,and the comprehensive performance is more and more strong.Traditional integer type PLL output frequency with low resolution can not meet the requirements of some high resolution system,however,the fractional N phase-locked loop can realize high resolution output with high frequency of crystal oscillator.Although the design of all digital phase locked loop(ADPLL)is flexible and portable,DPLL in main current high-perform demand application still become popular instead.In this paper,a wide output range fractional-N CPPLL has been propoed with the design flow of mix signal circuit.The main research works and initiatives embodied in the following four points:1.Sigma delta modulator based on SP-MASH technology.This paper introduces the design of a SP-MASH modulator with 12 bit input width.This architecture combines the advantages of MASH and HK-MASH structure both the output cycle sequence length is comparable to that of the HK-MASH structure,but also ensure the linear input such as MASH and also avoid the introduction of noise in the input.The effect of sigma delta modulator on phase noise of PLL is greatly reduced.The simulation results show that the SP-MASH designed in this paper has excellent noise shaping characteristics.Under the 50 MHz clock,the output background noise is lower than-200 dB,and the maximum output sequence length is 242.2.Multiloop high-sower-supply-rejection quadrature ring oscillator.The biggest feature of the QVCO is that the frequency is less sensitivity to variable supply in a certain range,able to avoid introduce LDO or other power management technology to improve the VCO supply rejection.The simulation result shows that the minimum normalized power sensitivity is about-46 dB.VCO uses the tuning method of VCR,the output frequency tuning range of VCO is about 440MHz-5.18 GHz,and the phase noise of frequency is-93dBc/Hz at 1MHz offset.3.High speed TSPC 4/5 dual modulu prescaler.The 4/5 prescaler using pseudo 2/3 prescaler structure reduce the delay on the critical path and thus greatly enhance the maximum operating frequency.It's operating range is from 4MHz to 5.5GHz.The maximum working frequency is 40% higher than that of the conventional structure under the same process.4.Dual charge pump loop structure based on regulated cascode technology.The regulated cascade structure greatly improves the dynamic range of the charge pump output.The current mismatch between the 0.2-1.6V control voltage is less than 0.6%.PLL uses a dual charge pump loop,which greatly reduces the locking time compared with the traditional single charge pump loop.This paper proposed wide range CPPLL based on Fractional-N divider designed in SMIC 180 nm CMOS process has output frequency tuning range between 1.5GHz-4.5GHz with the step of 12 KHz.The simulation results show that the phase noise of CPPLL is-94.36dBc/Hz@1MHz when the output frequency is 4.5GHz,and the maximum current is 25.8mA at 1.8V supply voltage,and the locking time beyond the whole output range is less than 8us.The design of the phase-locked loop in the same type of structure PLL output frequency range and lock time have certain advantages.