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Design Of Fractional Frequency Divider For IoT

Posted on:2021-02-23Degree:MasterType:Thesis
Country:ChinaCandidate:K HeFull Text:PDF
GTID:2518306476960359Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
The Internet of Things(IoT)is a communication network that enables different objects to communicate with each other.Since IoT applications require a large number of sensor nodes and a radio frequency transceiver with a phase-locked loop frequency synthesizer as the local oscillator is the core part of the IoT sensor node,it is necessary to reduce power consumption and area.The purpose of the thesis is to improve the performance of the frequency synthesizer applied in IoT by designing a fractional-N divider with low power consumption and less idle tones.First of all,the research background of the fractional-N divider and the problems faced by the design of the divider were summarized,and then different structures and working principles of programmable divider and modulator were introduced.On this basis,a fractional-N divider consisting of a programmable divider and a digital sigma-delta modulator was proposed.A improved 2/3 divider with only 5 branches was proposed as a synchronous circuit for the dual-mode prescaler which increased the operating frequency of the circuit by embedding a combinational logic circuit into the true single-phase clock divider and reduced power consumption by simplifying the trigger structure.In addition,in order to improve the purity of the output spectrum of the phase-locked loop,a 20-bit 3rd-order sigma-delta modulator with a maximum sequence length was proposed.By adding a feedback branch to the first-order modulator unit,the sequence length was extended to an order of 23×20,improving the noise performance of the modulator.Based on the TSMC 55nm CMOS process,the circuit design,the layout design and the chip test were done.The chip test results show that when the power supply voltage is 1V,the phase noise in different modes does not exceed-146d Bc/Hz@1MHz.The post-simulation results show that:when the power supply voltage is 1V,under different process angles,the power consumption of the fractional-N divider does not exceed 0.679m W,the operating frequency range is 1GHz?4.5GHz,the continuous frequency division range is 56?255,the phase noise of the programmable divider at 1k Hz frequency offset does not exceed-143d Bc/Hz,and the phase noise at 1MHz frequency offset does not exceed-160d Bc/Hz.
Keywords/Search Tags:phase-locked loop, programmable divider, sigma-delta modulator, maximum sequence length
PDF Full Text Request
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