Research Of Clock Deskewing And Clock Phase Optimization

The continuous scaling of microelectronic technology enables to keep on increasing system complexity and operating frequency. In particular, microprocessors are reaching frequencies in the order of GHz. Clock skew is recognized as one of the major limiting factor to keep on increasing system's speed. Nowaday, active deskew circuits are widely used for clock skew elimination.They can be largely classified into two methods: DLL/PLL deskewing and SMD deskewing. DLL/PLL methods achieve clock deskewing with good deskewing resolution, but suffer from slow locking, while SMD methods can achieve fast locking with limited deskewing resolution.In order to obtain an ideal deskewing circuit to solve the clock skew problem in a high-speed digital system, a mixed-mode deskewing circuit is proposed. The proposed deskewing circuit takes advantage of the architectural benefit given from a synchronous mirror delay in order to attain fast initial locking and combines a DLL tuning technique to achieve good deskewing resolution. It uses a DLL as a fine delay line and a SMD as coarse delay line. In a 0.18um CMOS process, its operation frequency range is 200MHz-600MHz at 1.8V. The die area is 0.03mm~2. The peak-to-peak jitter is 20ps. The SMD's locking time is 2 clock cycles and the DLL's locking time is less than 10 clock cycles.In additional, a novel 90-degree phase shifter and a duty-cycle corrector are developed with fast locking characteristics given from this mixed-mode deskewing architecture. In 0.13um CMOS process, the operation frequency ranges of phase shifter and duty-cycle corrector are 100MHz-600MHz and 200MHz at 1.2V. The peak-to-peak jitters are 40ps and 60ps. The locking times are both 3 clock cycles. For duty-cycle corrector, the acceptable duty-cycle of input signal ranges from 8% to 92% when the clock frequency is 400MHz.