Research On High Frequency Global Clock Wireless Distribution Technique Using On-chip Antennas

Nowadays, as CMOS technology scales gradually and chip integration grows rapidly, wired interconnection encounters great challenges in terms of delay and power consumption, which almost reaches the intrinsic limitations of metal materials. To solve these problems, wireless interconnect using on-chip antennas and electromagnetic waves for communication begins to emerge accordingly. Clock distribution implemented by wireless interconnect has the advantage of low delay and power consumption, saving metal and no need for modulation scheme, which turns to be a new solution for increasingly difficult clock distribution for microprocessors in the future. Therefore, wireless clock distribution not only handles clock distribution problem of microprocessors, but also can be possible to rapidly evaluate the potential of wireless interconnect for the developments of integrated circuits (ICs) in the future.According to the trend and challenges of clock distribution for microprocessors, an improved configuration for wireless distribution of high frequency global clock along with several key techniques are proposed in this thesis, based on the investigations of on-chip antenna characteristics and wireless interconnect technique. The critical components of wireless clock distribution system are also designed and realized in CMOS technology. Simulations are made to verify the whole proposed wireless clock distribution system. The main research achievements and innovations described in this thesis are summarized as follows:1. A modified configuration of wireless global clock distribution system for microprocessors is proposed, which consists of folded on-chip antenna pair, clock generation and receiving circuits as well as frequency divider. Phase-locked loop (PLL) is used to generate high frequency global clock, which ensures the performance of the whole wireless clock distribution system. This structure utilizes chip area effectively due to the folded on-chip antennas. Compared with conventional wired clock distribution systems, wireless clock distribution system with the proposed configuration has a lot of benefits, such as low delay, low static skew and jitter caused by process variations, less interference with low frequency digital circuits, no occupying metal layers, etc.2. A novel technique for improving on-chip antenna transmission gain is proposed. That is to say, a thin diamond layer is inserted between the silicon substrate and metal heat sink, which enhances the transmission gain of on-chip antenna pair greatly in a wide frequency band. In order to make antenna transmission performance predictable in real wireless interconnection systems, a modified electromagnetic wave propagation model involving a diamond layer and possible propagation paths are also proposed and compared with those of none dielectric situation. A 2mm long, 30μm wide linear on-chip dipole antenna pair is chosen for experimental object, simulations using HFSS are performed to verify the correctness and validity of this proposed technique. Meanwhile, the dependences of characteristics of integrated antennas applied for wireless interconnect on substrate resistivity, diamond thickness, antenna pair separation and dielectric variety have been studied. It is concluded that thinner diamond layer and higher resistivity substrate are helpful to improve antenna gain.3. Several experiential linear formulas for antenna pair gain and phase in interfering circumstances are proposed, and a set of design rules is concluded accordingly for on-chip antennas targeting wireless interconnections. As on-chip antennas do not operate in isolated surroundings, instead, various metal interfering sources possibly reside around them. In this thesis, these metal structures and placements are first classified, then the impacts of on-chip metal connective lines, power grids, heat sink along with packaging metals, and metal dummy fills on integrated dipole antenna characteristics have been investigated with qualitative analysis. Extensive simulations are performed by three-dimensional electromagnetic software HFSS to explore the interfering effects of various neighboring metal structures on the transmission gain, phase, impedance and radiation pattern for on-chip dipole antennas. Obtained experiential formulas and design rules can be used for guiding on-chip antenna design and its layout planning.4. Key circuits of wireless clock distribution such as high performance phase-locked loop (PLL), low noise amplifier (LNA) and 8:1 frequency divider have been designed and implemented in a 0.18μm CMOS process. PLL is realized using a LC oscillator, which can generate high frequency global clock with fine quality. The simulated phase noise achieves–116dBc/Hz at 3MHz frequency offset. A LNA for ultra-wide-band (UWB) application and a LNA for high frequency wireless clock distribution receiver have been both designed and realized. The former LNA employing common gate (CG) and common source (CS) stages achieves nearly constant power gain during 1.5GHz–5GHz, while the capacitive cross-coupling technique is introduced in the latter LNA for high frequency (above 10GHz) LNA design, remarkably improving LNA performance including gain enhancement, noise and nonlinearity reduction. Additionally, impedance conjugate matching is performed between the wireless clock receiver LNA and on-chip antennas. Therefore, optimal power transmission and overall performance are obtained. The 8:1 frequency divider is realized by source coupled logic (SCL), which can divide the received global clock rapidly and exactly. The maximum operation frequency of the proposed divider is up to 17GHz. 5. A 50% duty-cycle correction mechanism for local clock is proposed and implemented based on phase-blending. All circuits are realized in a purely digital manner. Higher reliability is achieved against process, voltage and temperature (PVT) variations due to the utilization of the synchronous mirror delay (SMD) technique. Moreover, the proposed correction mechanism eliminates complicated feedback loops often used in other correction methods, which further improves the correction capability. Experimental simulation results indicate that the correction operation finishes in only 4 clock cycles when the duty-cycle of input clock ranges from 10% to 90%, and the output local clock duty-cycle is 50%±2%.In summary, the wireless interconnect technique based on integrated antennas has been applied for clock distribution in microprocessors, and a wireless global clock distribution system is designed and implemented in this thesis. Simulated results show that the generated 11GHz global clock is first transmitted and received by on-chip antennas, then divided by eight to become 1.375GHz local clock with excellent skew and jitter performance. The achievements presented in this thesis have academic and practical values for advancing wireless interconnect applications and the developments of novel clock distribution techniques.