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Research And Design Of Cmos High-speed Serial Data Receiver

Posted on:2006-11-28Degree:DoctorType:Dissertation
Country:ChinaCandidate:L HuangFull Text:PDF
GTID:1118360155460593Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Serial data communication has gained wide application in network transmission, backplane transceiver and I/O interface. The ever-increasing demand for bandwidth has pushed serial communication data rates over multi-Gb/s. System integration, lower cost and low power requirements have made the CMOS the technology of choices for serial transceivers. The main work of the thesis is research and design of high-speed serial receiver.First, some design considerations of high-speed serial link are analyzed, which include influences of voltage noise and timing noise, transmission medium limitation and cable equalization, the type of phase detector in clock recovery. The two design examples given in this thesis are corresponding to these design considerations.Second, a fully integrated 1.25-Gbps CMOS Ethernet receiver with half-rate architecture is implemented in this work. The half-rate architecture is adopted to reduce the complexity of clock design and save power. A digitally programmable equalizer and an active continuous-time equalizer have been designed in the receiver front-end to compensate for the loss of the cable. An improved half-rate linear phase detector extracts the clock from the equalized data with smaller ripple on the oscillator control line, and hence lower jitter. A simple but practical deserializer de-multiplexed the retimed data with a synchronous Comma detection using the same dynamic cell. Based on 0.18μm CMOS process, simulation results show the above modifications are effective. Fabricated in a 0.18μm digital CMOS technology in an area of 1.2×1.0 mm2 (receiver), the circuit exhibits good results of equalized data, a 8ps rms jitter value of recovered clock, and dissipates 60 mV (core circuit) from a 1.8 V supply.Third, the architecture of quad channel 10Gbit Ethernet interface is investigated and the design of a 3.125-Gbps serial receiver is described. The multiphase clock generator and parallel sampling phase detector are used to reduce the speed requirement. Self-biased constant-gm biasing technique is used for charge-pump phase-locked loop to achieve low sensitivity to the variation of environments. The clock and data recovery circuit exploits 1/5-rate clock technique to facilitate the design of the ring oscillator and eliminate the need of 1:5 demultiplxer, thereby achieving low power consumption. The embedded current source is used in parallel output impedance control to eliminate an external resistor. The circuit has been designed and simulated in 0.18μm CMOS process. The power dissipation is 95 mW,...
Keywords/Search Tags:Serial Data Communication, Receiver, Half-Rate Clock Architecture, Dual Loop Structure, Parallel Sampling Technique, Equalizer, Data Sampler, Clock and Data Recovery, Phase Detector, Deserializer and Comma Detect
PDF Full Text Request
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