Simulation Analysis And Layout Design Of Clock System In A2GPSA A/D Converter

High precision clock signal is used in sample and hold circuit of high speed ADC.The clock signal of ADC is commonly an external input. The difference between theinput clock signal may lead to the change of clock signal of sample and hold circuit, andthe deviations between ideal value and sampling value, which resulting in theperformance degradation of the sample and hold circuit, may be caused. Furthermore, itmay result in the performance degradation of the whole A/D Converter. The internalstructure of clock signal circuit and non-ideal design may produce more noise and jitterof clock signal. The asymmetrical layout, and inter-channel device mismatch which iscaused by process variation, may lead to the inter-channel clock signal mismatch. Itmay result in the performance degradation of the multi-channel time-interleaved ADC.All about that, a clock signal system with less jitter and inter-channel clock phaseadjusting is required.This paper designs a clock signal circuit of8bit super high speed ADC at thefrequency of2GHz. It adopts a duty-cycle adjusting circuit, an inter-channel clockphase adjusting circuit, multi-channel clock generator to generate a clock signal with50%duty-cycle and accurate90degree inter-channel phase difference. Improved designof the delay cell decreases noise and jitters of the single-stage delay cell, and theduty-cycle adjusting circuit is optimized to Highly Precision at stable duty-cycle, andthe problem of inter-channel clock phase mismatch has been solved. The design ofExcellent Symmetry and Reasonable Layout brings less effect of noise and process tosusceptibility circuits. Furthermore, a system with less jitter and high matching has beenbuilt.The circuit is fabricated in0.18-μm standard COMS process technology, and it issimulated in the environment of EDA. The specific parameters of this circuit is:1.8Vpower supply voltage,20GHz maximum operating frequency,20％～80％duty cycleadjustment range,(501)％duty cycle of output clock,200fs time jitter,217mWdissipation. In short, the clock signal with low jitter and clock phase adjusting, andreached the needs of8bit high-speed A/D converter.