Research And Design On High-speed Clock Receiver Embedded With Duty Cycle Corrector

Recently,advances in semiconductor nano-CMOS fabrication technology and integrated circuits design techniques,have led to impressive growth of on-chip operating frequency.However,high-speed links in chip-to-chip communication are more vulnerable to non-ideal factors,such as transmission channel loss,noise and reflection,especially for the transmission of high-speed sensitive signals.The distortion of transmission waveform(amplitude attenuation,duty cycle distortion,increasing jitter,etc.)caused by the limited-bandwidth has severely constrained the overall performance at communication system hierarchy.Therefore,how to solve the high quality and efficiency transmission problem of high-speed clock has always been the focus of the industrial IC designers.Aims to address these challenges posed by high-speed clock receivers,a high speed low-jitter clock receiver based on continuous-time line-equalization(CTLE)and duty cycle correction is designed by using 40 nm standard CMOS process in this thesis.To solve the problem of signal integrity caused by the impedance discontinuity,an off-chip impedance matching network is designed at the front of clock receiver,and a reasonable differential termination is performed on-chip.The design of pre-equalizer in high-speed receiver combines the source degeneration trans-conductor CTLE and the active negative feedback CTLE,which greatly expands the effective bandwidth of the transmission channel,eliminates inter-symbol interference(ISI)and improves the high speed clock signal reception quality significantly.The design of duty-cycle corrector(DCC)within high-speed clock receiver bases on the common mode voltage feedback-compensation technique,which not only greatly improved the range and resolution of duty-cycle calibration compared with traditional schemes,but also minimized the output clock timing jitter.Both simple linear models of duty-cycle calibration loop stability and noise transfer function are provided in this thesis,and then analyzed the key loop parameters' influence to overall performance in details.To guarantee the reliability of duty cycle calibration,those key parameters can trim through registers reserved in circuits design.This paper provides a new solution for the design of high-speed clock receiver.Simulation results show that the proposed circuit can effectively receive off-chip high-speed clock signal from 1.5 GHz to 4 GHz.The DCC's calibration range is from 20% to 80%,the resolution of output clock duty is 50% ± 0.5%,and the RMS value of output clock timing jitter is 86 fs.The total area of high-speed clock receiver is about 0.06 mm2,and the power consumption is 17.6 mW.