Research On Key Technology Of Clock Data Recovery Of PAM4 High Speed Serial Signal

With the increase in global data traffic,the transmission speed of Ser Des(Serializer/Deserializer)systems have also been continuously increasing.To meet the speed requirements,IEEE 200 G and 400 G Ethernet standards,Optical Internetworking Forum OIF-CEI-5.0 standard,and PCIe6.0 standard all declare that Four-Pulse Amplitude Modulation(PAM4)will be adopted in the next generation of high speed communication technologies.The rate of PAM4 signal in the standards’ require is usually above 32 Gbps,therefore,it is particularly necessary to study Clock and Data Recovery(CDR)circuits at speeds higher than 32 Gbps to ensure accurate data transmission.In response to the design requirements of the PAM4 CDR circuits,the key technologies of clock data recovery of PAM4 high speed serial signals were studied,and a PAM4 CDR circuit was designed and completed.The main research content is as follows:(1)Due to the complex cross-architecture of PAM4 CDR circuits,so before select the architecture,analyzed the Ser Des systems architecture,CDR circuits architecture,and PAM4 CDR circuits architecture separately.Finally,the quarter-rate architecture was selected.Although this architecture is more complex than the full-rate architecture,it can reduce circuit powers consumption and bit error rate.The CDR circuit architecture based on a single Phase-Locked Loop was selected,which has advantages such as easy design,no need for a reference clock,and low power consumption compared to other architectures.The Bang Bang phase detected logic was selected to avoid the dead zone problem brought by linear phase detected logic,which makes it easier to work at high speed.Thus,the design adopted the quarter-rate Bang Bang phase detected type PAM4 CDR circuit architecture based on Phase-Locked Loop.(2)The architecture adopted in this design was divided into a level decision module and a CDR circuit based on Phase-Locked Loop according to their functions.Both parts were analyzed by modeling to provide design guidance of the PAM4 CDR circuit level implementation.The inherent jitter characteristic of the output of the former was obtained.For the latter,derive the transfer function of the simplest model and obtain a tradeoff relationship between loop parameters,and Simulink modeling was carried out to analyze the two characteristics of poor capture frequency capability and non-linearity that caused inherent jitter in the clock.(3)For the characteristic of poor capture frequency capability in the design architecture,a voltage to current converter charge/discharge current mismatch model that can assist frequency captured was proposed.The current mismatch model was verified through Simulink and implemented at the circuit level.(4)For the characteristic of non-linearity in the design architecture that causes inherent jitter in the recovered clock,an adaptive phase detected type voltage to current converter module was proposed.In the design architecture,it can sum up 9 sets of phase detect information output by the data/edge sampling module in parallel and dynamically output multistage currents,increasing the current in the unlocking stage to speed up the locking speed,and reducing the current in the locking stage to reduce jitter.Finally,based on the 40 nm CMOS process,a PAM4 CDR circuit was designed.Simulation results show that the PAM4 CDR circuit works normally under 40 Gbps serial data input,and the jitter of recovered clock peak-to-peak are 1.1 ps.Compared with traditional PAM4 CDR circuits,it has the characteristics of fast locking and small jitter,and meets the jitter tolerance standard specified in CEI-56G-VSR-PAM4.