Sample-and-Hold Circuit Design In 14Bit 250MS/s Pipelined ADC

Pipeline ADC was widely applied to mobile communication, military industry and medical instruments. Sample and hold circuit was one of the key components of pipeline ADC which affect the performance of the total system. Design of sample and hold circuit for the high speed and high accuracy pipeline ADC was important.In this thesis, a sample and hold circuit was applied as the first stage of a 14bit,250MS/s pipelined ADC. In the first place, the state-of-the-art in ADC research was described, and the industry development was focused on. The operation of time-interleaved pipelined ADC was introduced, errors in time-interleaved system like offset mismatch, gain mismatch and clock timing error were discussed. Design of a folded cascode OTA with gain-boosting technology, choosing the right value of sample capacitors in accordance with noise and consumption, and design of the switches were presented subsequently. OTA sharing technology between channels was applied. Divide-by-two circuit was given at the last place. It was specially applied to time-interleaved system for the purpose of clock phase alignment. Only one amplifier was applied in the total circuit, the two channels shared it with their working phase. Capacitor flip-around architecture was applied in each channel for the purpose of lower power dissipation, and the amplifier was easier to design at the same time.The layout design was based on SMIC 0.18μm 1P6M process. Post-simulation results revealed that when the input sinusoidal signal frequency was 10.7421875MHz, and the sample rate was 250MS/s, the SNDR and SFDR were 76.71dB and 89.47dB, ENOB was 12.47bit. Generally speaking, the performance of the sample and hold circuit meet the system requirement.