Research And Design Of A Sample And Hold Circuit For 16 Bit High Speed Pipelined ADC

Pipelined ADC achieves low power dissipation with the reasonable compromise between speed and solution. So the pipelined ADC is probably the optimal choice for high speed and high resolution ADCs. As the front-end interface of the pipelined ADC, the sample and hold circuit should achieve high linearity and low niose, which would influence the performance of the pipelined ADC. A sample and hold circuit for 16 bit 100 MSPS pipelined ADC is designed with 0.18?m, 1.8V power supply CMOS process in this thesis.First the basic principles and circuit architecture of the sample and hold circuit is introduced and the nonideal factors of the sample and hold circuit is analyzed. The improved architectures are presented to decrease the circuit errors. The capacitor flip-around sample and hold circuit is adopted as its perfect performance of low noise and wide bandwidth. A novel double gate-bootstrapping switch is designed to enhance the linearity and noise performance by raising the gate-source voltage of the switch transistor. The SFDR of the switch is increased by 3.6d B and the ENOB by 0.5bit. A high performance two-stage operational amplifier is designed to meet the requirements of gain, bandwidth, rate slew and linearity. The folded cascade op-amp is used in the first stage of the op-amp with gain-boosting op-amp to improve the gain and with the cross coupling and source feedback resistor to enhance the linearity of the op-amp. Two non-overlap clocks are designed to ensure the normal circuit timing. The swithed-capacitor dynamic bias technology is introduced to reduce the power dissipation of the sampling phase with the good settling performance. The power dissapaion of the op-amp is reduced by 36%. Spectre simulation of the sample and hold shows that the SFDR is 105.29 d B, the SNDR is 96.85 d B, the ENOB is 15.8bit and the power dissipation is 61 m W.The layout design is achieved based on the circuit design and simulation. The symmetrical layout is adopted for the sample and hold circuit to ensure the match of the differential circuit. The high match part is placed in the center, and the dynamic bias circuit and common-mode feedback circuit are placed far away from the op-amp. The input double transistors are surrounded by the guard ring to isolate the noise. The post-layout simulation results show the layout design is reasonable. At last, the measured results of the pipelined ADC show that the SFDR is 91.9d B,the SNDR is 74.2d B,and the ENOB is 12.04 bit. The DNL is within ±0.3LSB and the INL is within ±2.3LSB. The measured results indicate that the linearity of the sample and hold circuit meets the requirements of the pipelined ADC.