Design And Implementation Of JPEG Compression Encoder Based On FPGA

With the digital camera and other electronic products penetrate all aspects of human life,and image technology in aerospace,communications,biomedical and other areas of continuous application,these broad demand to stimulate the development of image compression technology.From JPEG to JPEG2000,and then to JPEG XR,research workers on image compression research has never stopped.While JPEG2000 and JPEG XR are superior to JPEG compression in some performance,in fact,JPEG compression is still the de facto mainstream technology.At the same time,in view of the rapid development of FPGA and its extensive application,its rich resource advantages and its strong parallel advantages are more and more popular,so in many high speed and real-time applications,researchers tend to Using FPGA to achieve image compression.In view of the JPEG compression in many areas of the application of grayscale images,so the realization of the JPEG compressor is designed for gray-scale images.This paper first introduces the background and significance of image compression and the current development of JPEG compression.Then,the design scheme of JPEG encoder in FPGA is given,and the process of JPEG compression basic system is introduced in detail.Secondly,a new implementation method is proposed for DCT transform and quantization of important algorithms in JPEG compression,and the simulation is verified by MATLAB.Then,according to the idea of modularity,the design and implementation of each module in FPGA are introduced.Finally,the test and verification of each module are given.The design uses Altera's Cyclone III series of chips,in the QuartusII 13.0 development environment to complete the design.For two-dimensional DCT transform modules,Using the class Chen algorithm,and make full use of FPGA parallelism and multiplier resources,to achieve a fast,stable DCT transform.Advise,quantitative module innovation can be achieved there are 9 different quantitative table to selection in the FPGA,and the entropy coding of DC/ AC coefficients is achieved by looking up the table.And then has carried out functional tests on each module,the image source data made MIF file for testing,and third-party software decoding,and finally proved to be able to display a complete picture.The test results show that the JPEG encoder achieves the intended functionality to achieve the design goal.