Fpga-based Jpeg Image Compression Chip Design

JPEG is a commonly used digital image compression algorithm officially known as ISO/IEC Standard 10918. JPEG has been widely used in multimedia communication for its excellent performance on compressing continouse tone still image.This thesis consists of designing and implementing a JPEG encoder system that is compatiable with JPEG baseline mode using FPGA (Field Programmable Gates Array) in standard hardware description language Verilog.The conception of JPEG baseline mode and the flow of FPGA design are firstly introduced. The traditional architecture of JPEG baseline mode encoder is presented. Disadvantages of traditional architecture are discussed and an enhanced architecture is proposed. Design principle, structures and Verilog implementations of modules in enhancement JPEG baseline mode encoder are described in detail in follow sections. Each section closed with the test results of respective module in timing verification.The hardware implementation results against real image input are presented and analyzed. Compressed images compressed by FPGA are compared to compressed images compressed by software, focusing on computing time and compress quality. Future research areas are suggested to improve the JPEG encoder performance.This thesis investigates the design technologies of complex SoC (System on Chip) by means of designing and implementing JPEG encoder operating in baseline mode. It provides preliminary study for large scale SoC.