The Research And Implementation Of JPEG Compression Encode Base On FPGA

With the development of the mobile terminal, multimedia, communications, image scanning technology, image becomes more widely available,so it's crucial of compression coding technology in large amounts of data storage and transmission during processing image. Meanwhile, the scale of single FPGA continues to expand, the complex digital signal processing system on FPGA chip has become realizable, Therefore the use of image compression on FPGA has become an inevitable trend. The application of JPEG still image compression standard, which is one of the main image compression standards , is very extensive now days. Research on the image compression of JPEG base on FPGA has a broad background.According to practical application and the design of IP core of image compression, The implementation of the JPEG compression algorithm on FPGA is realized. Firstly the JPEG compression standard's baseline system model is expounded, and then in the planning process, The rule of SOC design is adopted in the project, and the internal structure and the level of division of the whole system are given, and the detailed description about the HDL modules of the level of division'realization is made, ultimately, the overall completion of the final test is done. Reusable IP technology is used in project's design, based on the Xilinx's IP core for reusable development. After the research on the DCT(Discrete Cosine Transform),which is the core algorithm of JPEG standard, some improvement of the algorithm's realization on FPGA is made, then the DCT-based algorithm IP core based on distributed arithmetic is designed, well suits the device's structure. Through the optimization of structures and algorithms, the speed is improved, and the consumable of the chip's scarce resources is also reduced.The design is based on the Xilinx Virtex-II series FPGA hardware platform. And adopts ISE7.1 Compiler synthesis,finally is simulated and tested on Modelsim . The image source ,size of 352×288, in different grades of compression, is the tested successfully. The simulation results show that: JPEG compression base on FPGA cost less hardware resources,and can operate under the higher frequency, the design achieved a better utilization of resources and speed of the state, could be able to meet the requirements of real-time image compression. The design can be independent as JPEG encoder chip,also can be added to other digital systems, has some value.