Implementation Of JPEG Image Compression System Based On FPGA

While the large amount of data and the high requirement for real time in image compression make it not merely satisfy the implementation with Software Platform. FPGA now is widely used in the field of image compression because of the advantages in parallel computation and high-speed data processing. The primary works in this paper are realizing the system of JPEG image compression based on FPGA.According to the principles of JPEG compression, the system consists of four parts,2D-DCT module, quantization module, Zig-zag scanning module and entropy coding module. Adopting the row-column decomposition technique,2D-DCT module can be implemented with two1D-DCT and a transpose buffer. A fast algorithm for1D-DCT is proposed, thus minimizing computational complexity and saves much logic utilization in FPGA.1D-DCT computation is done in pipeline process and the ping-pang operation is exploited in the quantitation and Zig-zag scanning module. The entroy encoding part consists of runlength encoding followed by Huffman coding.The use of fast algorithm for1D-DCT speeds up the entire system and the essence of pipeline and ping-pang operation is to get a high speed with more area. The design of the entire system is aimed at obtaining the high speed and throughput and realizing the strong real-timely request of image compression system.The whole system are realized with Verilog HDL and emulated with software ISE12.3of Xilinx Inc.The hardware platform is Spartan-3E start kit board and each module and the system are tested on this board. The testing results show that the compression performance of the system can meet the practical requirements.