The FPGA Design Of JPEG-LS Image Lossless Compression IP Core

JPEG-LS (Joint Photographic Experts Group– Lossless) is an ISO/ ITU-T standard for continuous-tone still images lossless compression, which is mainly applied in satellites, medical, biology and other fields, such as wireless capsule endoscope for improving the diagnostic accuracy of Gastrointestinal disease. As a current important images lossless compression algorithm, JPEG-LS has a great compression capability with low complexity, and suitable for FPGA (Field Programmable Gate Array) implementation. Currently, there are a few of research projects in implementing image compression based on the JPEG-LS with FPGA at home and abroad. But ony the commercial core with high price and produced by the Xilinx Corporation takes this compression algorithm as reusable IP (Intellectual Property) core, it is fully packaged and has weak expansion in process of research and products developing.Based on the above, basic coding principle and concrete realizing procedures are deeply studied in this paper. Aiming at technology characteristics of this algorithm, application programming design model is got with high efficient on the PC platform, in which compression coding and lossless decoding on the 8 bit grayscale image with resolution of 512*512 within 1 second. In the test on 12 selected standard images, average compression ratio can reach to 2.04:1 or more. JPEG-LS image compression core is designed based on this reference model, and can complete the compression coding on a 8 bit grayscale image with resolution of 512*512 within 520us, but more than 500s are needed to realize compression coding in the application program designed on the PC platform. In these works above, the image encoder and decoder application programs on the PC are designed based on the C language, the image compression IP core are described accoding to adopt the VHDL hardware language, and design and verifying is got on the FPGA XC3S500E of the Spartan3E family produced by the Xilinx Corporation. All application programmings and RTL (Register Transmit Level) description files formed in research process of this subject can be applied in other design as independent API (Application Programming Interface) function and IP core, and can accumulate certain experiences for realizing the front end design of ASIC (Application Specific Integrated Circuit) chip of the JPEG-LS image lossless compression algorithm.