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Fpga-based Image Acquisition And Jpeg Compression System

Posted on:2010-10-17Degree:MasterType:Thesis
Country:ChinaCandidate:J L ZhangFull Text:PDF
GTID:2208330332478070Subject:Control theory and control engineering
Abstract/Summary:PDF Full Text Request
JPEG compression use the encoding techniques of high compression efficiency, and the JPEG standards committee optimize it, too. So, JPEG compressed image can effects-very high compression ratio with good visual.In recent years, It is widely used in internet image transmission as well as many image data storage, with the continuous improvement in computer speed and the JPEG compression algorithm continuously improved and mature.However, most is the software algorithm, when demanding very high compression speed, the software compression will not be able to meet people's needs.This is the demand that design a kind of JPEG compression algorithm by hardware implementation to solve the problem of insufficient speed.This design subject—FPGA-based video collection and JPEG compression system implement, it is proposed for solving this problem. The system uses Spartan3E series XCS500 devices belongs to XILINX Inc and completes CCD image data collection and JPEG compression encoding process in the ISE8.1 and EDK8.1 software environment. Functions module is designed by hardware description language (Verilog)In order to improve and upgrade for the system and implement completely system on a chip, this system uses the SOPC design and programs the software drivers by C language.In this paper, data collection and JPEG compression design are introduced in detail, and do functional simulation in every part of the logic functions.Paper finally summarizes the entire system.Data collection module is not only acquiring the image data of CCD,convering RAW to RGB and transfering and storing data by the open IP core in EDK, but also design the bus solution by asynchronous FIFO.JPEG compression module major use these technologies, for example,image sampling, DCT, quantization, zigzag scan, DPCM, RLE and Huffman coding.This design does not propose a new algorithm for JPEG and improvement. However, The use of hardware logic for image collection and implementation of JPEG algorithm is no doubt that has solved the problem of inadequate compression speed which is always troubling the people. It provides a convenient for image transmission and processing,also.In the field of the embedded image processing,it has real meaning.
Keywords/Search Tags:FPGA, Image Collection, JPEG
PDF Full Text Request
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