14-bit 500-MHz Self-calibration Current-Steering DAC Design

For the requirement of fast and high precision of signal propagation with the rapid improvement of information,a 14-bit 500MHz sampling rate DAC with current steering structure is designed in this paper.To reduce the effect of some non-ideal factors on the dynamic performance,a random selection calibration algorithm was used to calibrate the bit10-bit14 current source.This paper adapting 0.18um CMOS logic process,finally completed the DAC design with a digital calibration.The result as below:(1)The input signal involves bitl-bit5,bit6-bit9,bit10-bitl4 segment,the bit 1-bit5 binary is decoding,bit6-bit9,bit10-bit 14 are thermometer decoding(2)The limiting circuit before the switch control signal transmitted into the control switch.In this design the amplitude of the signal in the intersection of the signal and the control signal to reduce the glitch in the output can be effectively reduce.(3)To calibrate the current source of bit10-bit14,a random selection algorithm base on data Comparison and Sequence detection has been used.(4)In digital calibration unit the function of the algorithm was achieved through verilog,subsequently carry on the logic synthesis and physical layer.In conclusion the two DACs which with calibration and without calibration were simulated.When the input signal is 1 MHz at 500 MHz sampling rate,this CS-DAC without calibration has an SFDR of 74.3634 dB but with calibration the SFDR raise to 78.2798 dB and ef-fectively improve the performance of the dynamic characteristics.