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An Embedded 1.8V 10bit 120MS/s CMOS Current Steering Digital-to-Analog Converter IP Core

Posted on:2010-03-04Degree:MasterType:Thesis
Country:ChinaCandidate:G J ChenFull Text:PDF
GTID:2178360275997666Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
An Embedded 1.8V 10?bit 120?MS/s CMOS current steering digital-to-analog converter (DAC) IP core for wide band wireless local area network (WLAN) applications is described. In order to obtain better performance of low glitch energy and monotonicity, we adopt the segmented architecture to design the DAC. In the segmented architecture, the 4 least significant bits (LSB's) steer corresponding binary weighted current sources, while the 6 most significant bits (MSB's) are thermometer decoded and steer equally weighted current sources.DAC system modeling shows that the dynamic performance of the DAC is strongly dependent on the output impedance of DAC current sources. The gain boosting technique is applied to increase the output impedance of DAC current sources. A novel low swing, high crossing point currents switch driver is introduced to further improve dynamic performance by isolating digital switching noise from the analog output. We adopt hierarchical 2-order symmetrical switching sequences to compensate gradient error and symmetrical error.Based on the SMIC 0.18um mixed-signal CMOS technology, the DAC is simulated by the Spectre. The DAC can deliver up to 5mA full-scale current into a 50?load. With a supple of 1.8V, the integral and differential nonlinearity are measured to be less than 0.18LSB and 0.15LSB, respectively. When the output signal frequency is 1.01MHz and 49MHz at 120MHz sampling rate, the SFDR is measured to be 69dB and 58dB respectively. The die area is about 0.43mm×0.52mm.
Keywords/Search Tags:Digital-to-analog converter, Current steering, CMOS, High speed
PDF Full Text Request
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