Design Of High-Speed And High-Resolution Digital-to-Analog Converter With A Time Error Calibration System

Numerous applications of micro system in today’s life, business and biomedical field have drawn a bright future for data conveters, while at the same time put stringent requirements on them. Among them, Digital-to-Analog Conveters (DAC) are playing the role of bridging digital and analog world inside and outside the systems. It is no exaggeration to say that the power consumption, output performance and even the size of DAC have defined the reliability and practicability of the micro system it serves.Current Steering DAC is the most popular structure for high-speed and high-resolution DAC. It usually contains recievers, decoders, latches, switch drivers, switch array and current source array.This thesis presents a12-bit500-MSPS Current Steering DAC chip using TSMC0.18μm mixed-signal process. The DAC core includes LVDS recievers, decoders, latch array, switch driver array, switch array and current source array. According to post-simulation results, the DAC core is able to achieve SFDR above65dB across the whole Nyquist band.Static error due to mismatch in current sources and dynamic error due to mismatch in clock signals are two basic errors existing in Current Steering DAC, which call for carefully designed layout or additional calibration system. Dynamic calibration system is a system of which the goal is to remove the time error inside DAC. Its accuracy, efficiency and reliability in both detection and correction are highly considerated in its design. Another design rule for dynamic calibration system is that its existence can not bring in additional deterioration in DAC’s performance, such as power consumption and output performance.The designed DAC contains a dynamic calibration system to calibrate the time error inside the chip. Taking advantage of time difference amplifier and time-to-digital converter, the system is capable of detecting and correcting time error with a variance of2ps. In3to4periods, a time error less than500fs can be caliberated by the system. The maximum SFDR improvement brought by dynamic calibration system is lOdB.