Study And Implementation Of Calibration Techniques In DACs

As one of the indispensable interfaces in digital and analog systems, digital-to-analog converter (DAC) is an important part of modern communication systems and systems on chip. Current-steering DAC is widely used in high-speed and high-resolution systems, such as arbitrary waveform generators, communication transmitters and direct digital frequency synthesizers, with its intrinsic high speed and the ability to drive resistive loads directly.With the rapid development of digital signal processor (DSP) and complementary metal oxide semiconductor (CMOS) technologies, the dynamic performance and signal bandwidth of the DAC have become factors that limit the system performance. This thesis studies the design of current-steering DACs, analyzes the mechanism of the key factors that influence the spurious-free dynamic range (SFDR) and summarizes previous methods for these factors, which turns out to be a reference for DAC design. In addition, this thesis proposes a digital background calibration technique to overcome the mismatch of current sources. The proposed technique reduces the parasitic capacitance and gradient errors associated with small core area while guaranteeing the matching performance. The optimized calibration structure ensures uninterrupted data processing during the calibration.Using the proposed technique for higher dynamic range, a14bit500MS/s current-steering DAC is designed in0.13μm CMOS process. The DAC has an active area of0.69mm2and a chip area of3.1mm2. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are0.4LSB (Least Significant Bit) and1.2LSB, respectively, which indicates an intrinsic accuracy of nearly14-bit. At500MS/s, the SFDR is53.6dB/48.6dB for signals of11MHz/224MHz before calibration, and increased to70dB/50.3dB after calibration, respectively. The power consumption is165mW from a mixed power supply of1.2V and3.3V for digital and analog modules, respectively.