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Research And Design Of Digital To Analog Converter Applied To DDS

Posted on:2022-08-15Degree:MasterType:Thesis
Country:ChinaCandidate:X L HuangFull Text:PDF
GTID:2518306554470704Subject:Master of Engineering
Abstract/Summary:PDF Full Text Request
Direct digital frequency synthesis(DDS)is a key module in the field of radar systems and communications,and with the advent of the high-speed digital era,its development is rapid and its applications are becoming popular.The integration of high-performance DDS chips requires high-speed,high-precision digital-to-analog converter(DAC).Current steering DAC have the advantages of high speed,high accuracy and small area compared to other DAC types,and have become a popular mainstream structure for high-speed DACs,Widely used in DDS to implement digital to analog signal conversion.Firstly,the digital-to-analog converter structure is analysed and its advantages and disadvantages are compared.The current steering digital-to-analog converter can drive the load without a voltage buffer,increasing the overall circuit conversion rate.High-speed and high-precision performance requirements for DACs according to DDS,by analysing the impact of segmentation ratio on the circuit performance,the DAC designed in this paper adopts 6+6 segmented current steering structure,combining binary and thermometer coding methods,which has better matching,linearity and smaller area.The thermometer decoding uses deterministic decoding,which can reduce the complexity of the circuit compared to the traditional decoding circuit.The current source array uses a PMOS transistor common source and common gate structure to improve the output impedance and reduce noise interference,and the current source switch uses a differential switching structure to give the circuit a fast start-up time.The impact of the current source switch drive circuit on the overall circuit is analysed and a current source switch drive circuit with synchronous latching,limiting and cross-point reduction functions is designed to avoids simultaneous switching off of current source switches,reduce clock feedthrough and effectively reduce output signal burr.This paper is based on the simulation and verification of a 12-bit segmented current steering digital-to-analog converter in a standard 40 nm CMOS process.Simulation results show that at an analog voltage of 2.5V,a digital voltage of 1.1V,a sampling frequency of200 MHz and an input signal frequency of 99.609375 MHz,the spurious-free dynamic range(SDRF)can reach 62.8d B,the signal-to-noise ratio(SNR)is 59.14 d B,the build-up time is2 ns,the integral nonlinearity(INL)is ±1.13 LSB,differential non-linearity(DNL)is±0.12 LSB,and the overall average power consumption of the circuit is 31.5m W with an area of 0.16mm2.
Keywords/Search Tags:digital-to-analog converter, segmented structure, current steering, high speed and high precision
PDF Full Text Request
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