Research And Design Of Pipeline ADC For Broadband Wireless Communications

The enormous economic benefits grasped by the digital revolution is promoting the development of electronic system continuously in the direction of digitization and integration.The analog to digital converters(ADCs),being a critical passage linking the virtual digital world with the real analog world,has been playing a key role in the information society and the intelligent era.Among varieties of analog to digital converters,pipelined ADC can achieve highest accuracy at high conversion rates,and has been widely used in many fields,such as wireless communication system,medical imaging,radar,and so on.With the rapid developments of portable mobile communication equipment and low power SoC system,lower power has become the main development direction and market competition factor of ADCs.ADC is a mixed-signal system,whose digital part benefits a lot from continuous dimension shrink of CMOS process;while its high precision analog parts,especially the amplifiers in traditional pipelined ADCs,consume power hungrily in order to maintain same signal-to-noise ratio,which suffer much due to lower power supply voltage.New circuit technology and structures with appropriate optimization need to be introduced to reduce power consumption of the analog part.Based on analyses of pipelined ADC's structure,principle,and error sources,low power technology including SHA-less,scaling down,op-amp sharing between two channels,and low gain amplifiers with digital assisted calibration are applied in this thesis;A 12-bit 250-Msps dual-channel pipelined ADC that can be applied in broadband wireless communication,is designed,based on SMIC 55 LL CMOS process,with a supply voltage of 1.2V and a signal swing of 1.2V.Simulations after layout show that the dual-channel ADC can achieve SFDR of 75 dB under 250 Msps with input signal frequency of 110 MHz,and its total power consumption is 125 mW.