Background digital calibration for interstage gain errors and memory effects in pipelined analog-to-digital converters

High-speed high-linearity ADCs are required for many modern communication applications and often require implementation in digital CMOS processes. Many of the changes introduced to these processes in order to decrease the cost and increase the performance of digital circuits, such as reduced supply voltages and new dielectric materials, make the design of precision analog circuits, such as high-resolution ADCs, more difficult. Interstage gain inaccuracy and signal dependence can often limit the linearity of pipelined ADCs. A digital calibration technique is proposed that can correct for interstage gain inaccuracy and signal dependence in the background. This technique requires only a small increase in analog complexity and reduces dependence on input signal statistics when compared to similar published techniques. The analysis and design of pipelined ADCs generally assumes that each stage of the pipeline is memoryless. Circumstances are found where this assumption may not be true. Switched-capacitor implementations of pipelined ADCs contain several sources of memory errors, including capacitor dielectric absorption and relaxation, incomplete stage reset at high clock rates, and charge stored in parasitic capacitance when op amps are shared between subsequent pipeline stages. These sources of memory errors are described and a unified model is presented for their effect. The effect of memory errors on ADC linearity is analyzed and simulated, showing how these errors can limit the linearity of a pipelined ADC. Two digital background calibration techniques are introduced that can correct for these memory errors. These are the first calibration techniques that can correct for memory errors in pipelined ADCs.