A Study Of Digital Background Calibration Of Harmonic Distortion In Pipelined ADCs

As the interface between digital circuits and analog circuits, the ADCs(Analog-to-Digital Converters) play an very important role in integrated circuits designs. Pipelined ADCs works fast and accurately, so it is used in voice and video process, signal detection and communication widely. But due to the existence of some non-ideal factors, such as the offset of comparator, mismatch of capacitance components, varies of outside environment or temperature, and op-amp limited gain effect etc. There will be some non-ignorable errors in pipelined ADCs, which would lower the performance of the ADCs, and may even output the wrong results. Therefore, an effective calibration technique is highly needed in pipelined ADCs design.Pipelined ADCs are very sensitive to distortion introduced by the residue amplifiers, especially in their first few stages. However, residue amplifiers distortion tends to increase power consumption in practice, so the residue amplifiers usually become the dominate consumers of power in high resolution pipelined ADCs. This paper gives detailed analysis on harmonic distortion of residue amplifiers in pipelined ADCs firstly, and then combined with the operating principle of the pipelined ADCs systemic digital background calibration technique is obtained and its validity is testified. The previous relevant papers just give simple arguments and final results, but it is very important and necessary from mathematic point to analyze, deduce and model the harmonic distortion of residue amplifiers in depth and great detail, which provides the most important basic theory of building the digital background calibration model accurately.The digital background HDC technique is presented to cancel the harmonic distortion introduced by residue amplifiers. A pseudo random sequence is injected to the signal path to measure the distortion and to control the calibration signal, and then the distortion will be canceled at digital output port. Only singled-order distortion introduced by residue amplifiers is considered firstly in this paper, analysis and deductions are presented in detail, so the algorithm is tested of its function, and then multi-order distortion is considered, but the higher orders will have an effect on lower order coefficients, which means these coefficients would deviate from the wanted values and should be corrected. Pipelined ADCs with HDC technique is modeled by MATLAB SIMULINK according to the algorithm, behavioral simulation results shows that when the sample rate is 100 MHZ, the pipelined ADCs with HDC can achieve ENOB of 14 bit, SNDR grows from 59.1d B to 82.9d B and SFDR grows from 65.6d B to 96.8d B, which can fulfill the requirements in practice.