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Researtch On Design Techniques Of High Performance Pipelined Analog To Digital Converters

Posted on:2015-06-12Degree:DoctorType:Dissertation
Country:ChinaCandidate:C J FanFull Text:PDF
GTID:1108330476953940Subject:Electronic Science and Technology
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Pipelined Analog to Digital Converters(ADC) are widely used as key devices in various electronic systems, such as wireless base stations, image sensors, and radars, converting voltage, current, and even time into digital codes for further digital processing. Recently, as the abilities of digital processors have been greatly improved due to the advances in manufacturing technologies of modern CMOS integrated circuits, a lot of systems move their functions that were traditionally achieved by analog blocks into the digital domain, and require ADCs with higher resolutions, sampling rates, input signal bandwidth, and lower power consumptions; meanwhile, the CMOS technology becomes more and more popular for analog circuit design in large scale mixed signal chips for integration, and thus low cost.Through theoretical analysis and experiment, this thesis studies design and implementation techniques of high speed, high resolution, and low power ADCs in deep sub-micron CMOS technology. The focuses of this work are on pipelined ADC architecture, high performance analog blocks, digital calibration algorithms, and testing environment setup, wherein novel design techniques are proposed in both architectural and circuit levels, besides, two novel digital background calibration techniques for nonlinear inter-stage gain errors are introduced, trying to overcome the disadvantages of short channel devices. The main contributions of this thesis are briefly stated below:A comparison between different pipeline architectures is made; special attention has been paid to the SHA-less ones featured by low noise and power. Behavioral simulations are performed on architectures with different distributions of resolution, power consumption, and noise contributions among the pipeline stages, which finally arrive at an optimized choice in regard to noise and power. To cope with the special issues in SHA-less architecture, a suitable timing scheme is designed, and a double-reference method is proposed for power efficiency of backend stages.Proper design techniques for key analog modules such as sampling network, clock generator, Flash ADCs, and OpAmps are chosen by careful analysis and comparison of systematic SPECs and their circuit approaches. A novel optimization criterion has been developed to assist the design of low power operational amplifiers. By boosting bulk voltages of the sampling switches and two additional switches connecting the top plates of both the differential sampling capacitor arrays, and minimizing the transistor size, the sampling network’s bandwidth and linearity at high frequencies are improved. The problem of comparator kick-back noise is circumvented by timing control in Flash ADCs, which allows a simplified design process, accelerates the comparison, and saves power.The thesis also pays attention to the traditional calibration technique for linear errors in pipelined ADCs, and applies it to correct the mismatch between two voltage references, which plays a key role in this low power design. In addition, two novel digital calibration techniques for nonlinear inter-stage gain errors in pipelined ADCs are proposed, compared with the prior arts, these techniques correct for larger nonlinearities, converge faster, and are more adaptable to different input signal distributions, pointing out a potential solution to high speed, high resolution ADC design in advanced processes.Based on the above techniques, a 16 bit, 100 MSPS pipelined ADC is designed and fabricated in TSMC 0.18μm CMOS process, and a complete evaluation environment is set up for high speed, high resolution ADC testing. The chip uses 1.8V supply, and occupies a die area of 2.45mm×4.9mm. Experimental results show that the chip consumes less than 300 mW when clocked at 100MHz; the thermal noise floor is at-75.6 dBFS. With full-scale(2Vpp) input, the signal to noise and distortion ratio(SNDR) reaches a maximum of 75.4 dB, corresponding to an effective number of bits(ENOB) of 12.23, and maintains above 72.8 dB with input frequency under 150MHz(the 3rd Nyquist Band); the spurious free dynamic range reaches above 90 d B, and maintains above 87 d B with input frequency under 150 MHz. The 16 bit ADC has a differential nonlinearity(DNL) of-0.81/+0.22 LSB, and an integral nonlinearity(INL) of-3.75/+1.75 LSB. Figure of merit(FOM) of this converter is 0.62pJ/step, which is competitive among related reports. In addition, this chip supports power-down mode, outputs complementary binary code in CMOS logic, provides an SPI interface for register configurations and a reference voltage pin, making it qualified wireless base stations applications.
Keywords/Search Tags:pipelined ADCs, SHA-less frontend, switched capacitor, bottom plate sampling, bootstrapped switch, clock jitter, digital calibration algorithm, nonlinear error calibration
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