Design Of 16-bit 200MSPS Current Steering DAC Based On Dynamic Error Calibration

The demand of high speed,high precision DACs with high dynamic performance is increasing gradually with the development of world industry.Although the domestic semiconductor starting platform is low,the technology accumulation is less,a large number of excellent high-speed,high-precision DAC design has emerged with the relentless efforts of domestic scientific research.In response to the torrent of times and needs,this paper designed a 16-bit 200 MSPS current-steering DAC based on the 40 nm CMOS process.First of all,the basic concept and structure of the DAC is well explained,respectively.The advantages and disadvantages of different DAC with different architectures and its specific application environment is well introduced and compared.According to the design specification of this paper and the mainstream architecture of the high speed,high precision DAC,the current steering segmented DAC is selected as the basic architecture in this paper.Then,this paper studies the non-ideal factors which influence the dynamic and static performance of the current steering DAC,and finds out the corresponding calibration scheme.During the research,a sufficient formula is given to prove some non-ideal factors with references.The study of the calibration algorithm provides a more theoretical guidance for the selection of the calibration algorithm in this paper.Based on the calibration algorithm which is studied before,a new calibration algorithm is proposed.The dynamic mismatch sensor circuit is used to detect,quantify and match the dynamic error of the current source,and the dynamic performance of the 16-bit 200 MSPS segmented DAC is correspondingly improved.The DAC segmentation scheme,the unit current cell,the low swing high speed differential switch driver,LVDS receiver and the dynamic mismatch sensor is completed based on the standard 40 nm CMOS process,the proposed calibration algorithm and the performance parameters of the 16 bit 200MSPS DAC.Finally,the layout of the key modules,such as current source,low swing high speed differential switch driver and LVDS circuit,is completed based on the standard 40 nm CMOS process,and the 16-bit 200 MSPS DAC is verified.The results show that the SFDR of the DAC is 93.062 dB under the output signal frequency of 17.1875 MHz and the sampling clock frequency of 200 MHz,the overall power dissipation is 120 mW,the layout area of the DAC core is 42 mm.