Research And Design Of A 12-Bit 300MS/s Segmented Current-Steering DAC In 0.18?m CMOS Process

Digital-to-Analog Converter(DAC)plays an extremely important role in radar,electronic warfare,wired or wireless communications and many other fields.In the field of communications,as a key part of a transmission system,DAC seriously restricts the improvement of the whole system's performance.In order to keep up with the development of DSP systems,the research and design of high-speed and high-precision DACs have become an important trend.As we all know,binary-coded DACs have a simple structure,fast speed,but poor linearity,while thermometer-coded DACs have high linearity,but a complex structure and slow transition speed.To meet the requirements of high speed and high precision at the same time,segmented current-steering DACs are usually used to take into account the advantages of the two decoding circuits.Based on the above theory,a 12-bit current-steering DAC with a segmented mode of '8 MSBs+4 LSBs' and a sampling rate of 300MS/s is proposed.For traditional segmented current-steering DACs,the least significant bits are often realized by a binary-coded DAC,while the most significant bits are realized by a thermometer-coded DAC.Firstly,since all switches of a binary-coded DAC are involved during the period of the mid-code transition,which makes the glitches of the DAC output large and the nonlinearity of the system bad,the 4 LSBs of the DAC in this paper are realized by a split-coded one.The split-coded DAC can not only make up for the shortcomings of a binary-coded DAC mentioned above,but also has a simple decoding circuit compared with a thermometer-coded DAC.Secondly,to further improve the dynamic performance of the system,a technique called Random Rotation-based Binary-weighted Selection(RRBS)follows the split-code decoding circuit.In this way,without changing the weights of current sources corresponding to each split code,the activities of switching are randomized to increase the matching of LSBs' current sources.Moreover,due to the complex structure and high transmission delay of the traditional thermometer-code decoding circuit,a new interpretation of its truth table has been done,binary input codes are considered references and dichotomizd one by one from the high bit to the low bit,and a new thermometer-code decoding circuit is designed.Eventually,the latches are used to synchronize the timing sequence of different decoding circuits,which can avoid the errors of the DAC output.In the meantime,the switches are in the form of differential pairs to suppress even order harmonics,and the current sources are adopted by the structure of the PMOS cascode to increase the output impedance.In order to make the current sources close to ideal states,a bias circuit with wide swing and high output-impedance is designed,including a bandgap reference circuit,a voltage to current circuit and a current-source bias circuit.According to post simulations in 0.18?m CMOS process,the DNL and INL of the DAC are±0.08LSB and-0.1?1LSB,respectively.When the frequency of the sine wave input signal is 1.098633MHz,the SFDR,ENOB,SNDR and THD of the DAC are 81.44dB,11.22bit,69.33dB and-80.68dB,respectively.Moreover,when the input signal frequency is 149.9268MHz,the SFDR,ENOB,SNDR and THD are 64.97dB,10.38bit,64.27dB and-64.89dB,respectively.With the single-ended load resistance of 50? and the power supply voltage of 1.8V,the average power consumption is 51.43mW.